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84143012X PDF预览

84143012X

更新时间: 2024-11-04 19:55:27
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
7页 113K
描述
ALS SERIES, DUAL 4-INPUT AND GATE, QCC20, 0.358 X 0.358 INCH, 0.100 INCH HEIGHT, LCC-20

84143012X 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.52Is Samacsys:N
系列:ALSJESD-30 代码:S-CQCC-N20
长度:8.89 mm逻辑集成电路类型:AND GATE
功能数量:2输入次数:4
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT APPLICABLE
传播延迟(tpd):18 ns认证状态:Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT APPLICABLE
宽度:8.89 mmBase Number Matches:1

84143012X 数据手册

 浏览型号84143012X的Datasheet PDF文件第2页浏览型号84143012X的Datasheet PDF文件第3页浏览型号84143012X的Datasheet PDF文件第4页浏览型号84143012X的Datasheet PDF文件第5页浏览型号84143012X的Datasheet PDF文件第6页浏览型号84143012X的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ ꢇꢆ ꢈꢉ ꢊ  
ꢊ ꢃ ꢈꢀꢋꢌꢍ ꢎ ꢌꢀꢏ ꢁꢅꢄꢐ ꢑꢁ ꢑꢒꢀ ꢓꢔ ꢁꢌꢐꢏ ꢅꢑ ꢒꢁꢋ ꢎꢐ ꢌꢁꢕ ꢑ ꢀꢅꢔ ꢖꢖ ꢌꢋꢑ ꢐ  
SCLS599 − NOVEMBER 2004  
D OR PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
D
Qualified for Automotive Applications  
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
L
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
Q
Q
Q
Q
M
J
H
I
Q
N
Q
Q
F
12 CLR  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive up to Ten LSTTL Loads  
E
11  
10  
9
Q
CLKI  
G
Q
CLKO  
CLKO  
D
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
CC  
GND  
Low Input Current of 1 µA Max  
Allow Design of Either RC- or  
Crystal-Oscillator Circuits  
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74HC4060 device consists of an oscillator section and 14 ripple-carry binary counter stages. The  
oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the  
clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO  
goes high and CLKO goes low) and resets the counter to zero (all Q outputs low).  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Reel of 2500  
Reel of 2000  
SN74HC4060QDRQ1  
SN74HC4060QPWRQ1  
HC4060Q  
HC4060Q  
−40°C to 125°C  
TSSOP − PW  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
FUNCTION  
CLK  
CLR  
L
No change  
Advance to next stage  
All outputs L  
L
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢋꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢘꢡ  
ꢟꢣ  
ꢔꢙ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢꢡ  
ꢟꢘ  
ꢛꢡ  
ꢙꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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