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8405601DX PDF预览

8405601DX

更新时间: 2024-11-04 13:00:59
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
20页 725K
描述
HC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14

8405601DX 技术参数

生命周期:Active零件包装代码:DFP
包装说明:CERAMIC, DFP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.49Is Samacsys:N
系列:HCJESD-30 代码:R-GDFP-F14
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.0052 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:21000000 ns传播延迟(tpd):265 ns
认证状态:Qualified筛选级别:MIL-STD-883
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

8405601DX 数据手册

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SN54HC74, SN74HC74  
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCLS094D – DECEMBER 1982 – REVISED JULY 2003  
SN54HC74 . . . J OR W PACKAGE  
SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 40-µA Max I  
CC  
1CLR  
1D  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
Typical t = 15 ns  
pd  
±4-mA Output Drive at 5 V  
1CLK  
1PRE  
1Q  
12 2D  
Low Input Current of 1 µA Max  
11  
10  
9
2CLK  
2PRE  
2Q  
description/ordering information  
1Q  
8
The ’HC74 devices contain two independent  
D-type positive-edge-triggered flip-flops. A low  
levelatthepreset(PRE)orclear(CLR)inputssets  
or resets the outputs, regardless of the levels of  
the other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the setup  
time requirements are transferred to the outputs  
on the positive-going edge of the clock (CLK)  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of CLK.  
Following the hold-time interval, data at the  
D input can be changed without affecting the  
levels at the outputs.  
GND  
2Q  
SN54HC74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
2CLK  
1PRE  
NC  
15 NC  
14  
2PRE  
1Q  
9 10 11 12 13  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC74N  
SN74HC74N  
SN74HC74D  
SN74HC74DR  
SN74HC74DT  
SN74HC74NSR  
SN74HC74DBR  
SN74HC74PW  
SN74HC74PWR  
SN74HC74PWT  
SNJ54HC74J  
HC74  
–40°C to 85°C  
SOP – NS  
HC74  
HC74  
SSOP – DB  
TSSOP – PW  
HC74  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC74J  
SNJ54HC74W  
SNJ54HC74FK  
–55°C to 125°C  
SNJ54HC74W  
SNJ54HC74FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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