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8404201CAS2035 PDF预览

8404201CAS2035

更新时间: 2024-09-24 21:06:31
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
7页 124K
描述
HC/UH SERIES, TRIPLE 3-INPUT NOR GATE, CDIP14, 0.300 INCH, CERAMIC, DIP-14

8404201CAS2035 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.19系列:HC/UH
JESD-30 代码:R-GDIP-T14逻辑集成电路类型:NOR GATE
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):135 ns
认证状态:Not Qualified筛选级别:MIL-STD-883
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

8404201CAS2035 数据手册

 浏览型号8404201CAS2035的Datasheet PDF文件第2页浏览型号8404201CAS2035的Datasheet PDF文件第3页浏览型号8404201CAS2035的Datasheet PDF文件第4页浏览型号8404201CAS2035的Datasheet PDF文件第5页浏览型号8404201CAS2035的Datasheet PDF文件第6页浏览型号8404201CAS2035的Datasheet PDF文件第7页 
SN54HC27, SN74HC27  
TRIPLE 3-INPUT POSITIVE-NOR GATES  
SCLS088B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC27 . . . J OR W PACKAGE  
SN74HC27 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
1C  
1Y  
3C  
2A  
description  
2B  
These devices contain three independent 3-input  
NOR gates. They perform the Boolean function  
Y = A + B + C or Y = A B C in positive logic.  
2C  
10 3B  
9
8
2Y  
3A  
3Y  
GND  
The SN54HC27 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC27 is characterized for  
operation from –40°C to 85°C.  
SN54HC27 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
3C  
2A  
NC  
2B  
4
5
6
7
8
INPUTS  
17  
16  
OUTPUT  
Y
A
H
X
X
L
B
X
H
X
L
C
X
X
H
L
15 NC  
14  
9 10 11 12 13  
NC  
2C  
L
L
3B  
L
H
NC – No internal connection  
logic symbol  
1
1A  
1B  
1C  
2A  
2B  
2C  
3A  
3B  
3C  
1  
2
12  
1Y  
13  
3
4
6
2Y  
5
9
10  
11  
8
3Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, and W packages.  
logic diagram (positive logic)  
A
B
C
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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