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83336-21 PDF预览

83336-21

更新时间: 2024-10-28 08:08:39
品牌 Logo 应用领域
PSEMI /
页数 文件大小 规格书
14页 277K
描述
3.0 GHz Integer-N PLL for Low Phase Noise Applications

83336-21 数据手册

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PE83336  
Product Specification  
Pin No.  
Pin  
Interface  
Mode  
Type  
Description  
(44-lead  
Name  
CQFJ)  
Monitor pin for main divider output. Switching activity can be disabled through  
enhancement register programming or by floating or grounding VDD pin 31.  
30  
31  
32  
33  
fp  
ALL  
Output  
VDD-fp  
Dout  
VDD  
ALL  
(Note 1)  
Output  
VDD for fp. Can be left floating or connected to GND to disable the fp output.  
Serial,  
Parallel  
Data Out. The MSEL signal and the raw prescaler output are available on Dout through  
enhancement register programming.  
ALL  
(Note 1)  
Same as pin 1.  
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kseries resistor.  
Connecting Cext to an external capacitor will low pass filter the input to the inverting  
amplifier used for driving LD.  
34  
Cext  
ALL  
Output  
35  
36  
37  
38  
VDD  
ALL  
ALL  
ALL  
ALL  
(Note 1)  
Output  
Same as pin 1.  
PD_D  
PD_U  
VDD-fc  
PD_D is pulse down when fp leads fc.  
PD_U is pulse down when fc leads fp.  
VDD for fc can be left floating or connected to GND to disable the fc output.  
(Note 1)  
Output  
Monitor pin for reference divider output. Switching activity can be disabled through  
enhancement register programming or by floating or grounding VDD pin 38.  
39  
fc  
ALL  
40  
41  
42  
GND  
GND  
fr  
ALL  
ALL  
ALL  
Ground.  
Ground.  
Input  
Reference frequency input.  
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high  
impedance, otherwise LD is a logic low (“0”).  
43  
LD  
ALL  
Output  
Serial,  
44  
Enh  
NC  
Input  
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.  
No connection.  
Parallel  
N/A  
ALL  
Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.  
V
DD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc  
outputs.  
Note 2: All digital input pins have 70 kpull-down resistors to ground.  
File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS  
Copyright Peregrine Semiconductor Corp. 2003  
Page 4 of 14  

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