Port Synchronizer for IEEE 1588 and
10G/ 40G/ 100G Synchronous Ethernet
82P33741
Datasheet
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APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
APLL3 generates 10G/40G/100G Ethernet, WAN-PHY and LAN-PHY
frequencies
Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
The I2C slave interface can be used by a host processor to access the
control and status registers
The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset; APLL3 must be configured
via the I2C slave interface
Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
Differential outputs OUT10 and OUT11 output clocks with frequencies
up to 650 MHz
Single ended outputs OUT1, OUT2, and OUT7 output clocks with fre-
quencies between 1 PPS and 125 MHz
Single ended outputs OUT8 and OUT9 output clocks N*8kHz multi-
ples up to 100 MHz
DPLL1 and DPLL2 support independent programmable delays for
each of IN1 to IN12; the delay for each input is programmable in steps
of 0.61 ns with a range of ~±78 ns
The input to output phase delay of DPLL1 and DPLL2 is programma-
ble in steps of 0.0745 ps with a total range of ±20 s
The clock phase of each of the output dividers for OUT1 to OUT7 is
individually programmable in steps of ~200 ps with a total range of +/-
180°
HIGHLIGHTS
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DPLL1 and DPLL2 can be used on line cards to manage the genera-
tion of synchronous port clocks and IEEE 1588 synchronization sig-
nals based on multiple system backplane references
DPLL3 can be used on line cards to select incoming line clocks for
use on system backplanes; it can also be used for general purpose
timing applications
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APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate
IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals
APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and
generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for:
10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R
Fractional-N input dividers support a wide range of reference frequen-
cies
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DPLLs, APLL1 and APLL2 can be configured from an external
EEPROM after reset
FEATURES
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Differential reference inputs (IN1 to IN6) accept clock frequencies
between 2 kHz and 650 MHz
Single ended inputs (IN7 to IN12) accept reference clock frequencies
between 2 kHz and 162.5 MHz
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
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Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G/
40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS
frequencies
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1149.1 JTAG Boundary Scan
144-pin CABGA green package
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APPLICATIONS
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Synchronous clock generation for 10/40G and lower rate, Ethernet,
PON OLT and SONET/SDH line card
Access routers, edge routers, core routers
Carrier Ethernet switches
Multi-service access platforms
PON OLT
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Any reference inputs (IN1 to IN12) can be designated as external sync
pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-
able reference clock input
FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
DPLL1 and DPLL2 can be configured with bandwidths between 18 Hz
and 567 Hz
DPLL1 and DPLL2 lock to input references with frequencies between
2 kHz and 650 MHz
DPLL3 locks to input references with frequencies between 8 kHz and
650 MHz
LTE eNodeB
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DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1
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DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT8 and OUT9
APLL1, APLL2 and APLL3 can be connected to DPLL1 and DPLL2
©2017 Integrated Device Technology, Inc.
1
September 15, 2017
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