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821024J8 PDF预览

821024J8

更新时间: 2024-11-10 20:06:03
品牌 Logo 应用领域
艾迪悌 - IDT PC电信电信集成电路
页数 文件大小 规格书
14页 713K
描述
PCM Codec, A/MU-Law, 1-Func, CMOS, PQCC32, PLASTIC, LCC-32

821024J8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFJ
包装说明:QCCJ, LDCC32,.5X.6针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.07
压伸定律:A/MU-LAW滤波器:YES
最大增益公差:0.35 dBJESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.97 mm
线性编码:NOT AVAILABLE湿度敏感等级:1
功能数量:1端子数量:32
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:3.56 mm
子类别:Codecs标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:11.43 mm
Base Number Matches:1

821024J8 数据手册

 浏览型号821024J8的Datasheet PDF文件第2页浏览型号821024J8的Datasheet PDF文件第3页浏览型号821024J8的Datasheet PDF文件第4页浏览型号821024J8的Datasheet PDF文件第5页浏览型号821024J8的Datasheet PDF文件第6页浏览型号821024J8的Datasheet PDF文件第7页 
QUAD NON-PROGRAMMABLE  
PCM CODEC  
821024  
DATASHEET  
DESCRIPTION  
FEATURES  
4 channel CODEC with on-chip digital lters  
Selectable A-law or μ-law companding  
Master clock frequency selection: 2.048 MHz, 4.096 MHz or  
8.192 MHz  
The IDT821024 is a single-chip, four channel PCM CODEC with on-  
chip lters. The device provides analog-to-digital and digital-to-analog  
conversions and supports both a-law and μ−law companding. The digital  
lters in IDT821024 provides the necessary transmit and receive ltering for  
voice telephone circuit to interface with time-division multiplexed systems.  
All of the digital lters are performed in digital signal processors operating  
from an internal clock, which is derived from MCLK. The xed lters set  
the transmit and receive gain and frequency response.  
- Internal timing automatically adjusted based on MCLK and frame  
sync signal  
Separate PCM and master clocks  
Single PCM port with up to 8.192 MHz data rate (128 time slots)  
Transhybrid balance impedance hardware adjustable via external  
components  
Transmit gains hardware adjustable via external components  
Low power +5.0 V CMOS technology  
In the IDT821024 the PCM data is transmitted to and received from the  
PCM highway in time slots determined by the individual Frame Sync signals  
(FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both  
Long and Short Frame Sync modes are available in the IDT821024.  
The IDT821024 can be used in digital telecommunication applications  
such as PBX, Central Ofce Switch, Digital Telephone and Integrated  
Voice/Data Access Unit.  
+5.0 V single power supply  
Package available: 32 pin PLCC, 44 pin TQFP  
FUNCTIONAL BLOCK DIAGRAM  
821024 REVISION A JUNE 25, 2014  
1
©2014 Integrated Device Technology, Inc.  

821024J8 替代型号

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PCM Codec, A/MU-Law, 4-Func, CMOS, PQCC32

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