Datasheet > 7KL0641DAHV02

7KL0641DAHV02

更新时间： 2024-11-12 01:17:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		动态存储器
页数	文件大小	规格书
29页	770K
描述
HyperRAMâ¢ Self-Refresh DRAM 3.0V/1.8V 64 Mb (8 MB)

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数据手册

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7KL0641DAHV02 数据手册

ADVANCE

S27KL0641, S27KS0641

HyperRAM^™Self-Refresh DRAM

3.0V/1.8V 64 Mb (8 MB)

Distinctive Characteristics

HyperBus™ Low Signal Count Interface

High Performance

 3.0V I/O, 11 bus signals

– Single ended clock (CK)

 1.8V I/O, 12 bus signals

– Differential clock (CK, CK#)

 Chip Select (CS#)

 Up to 333MB/s

 Double-Data Rate (DDR) - two data transfers per clock

 166-MHz clock rate (333 MB/s) at 1.8V V_CC

 100-MHz clock rate (200 MB/s) at 3.0V V_CC

 Sequential burst transactions

 Configurable Burst Characteristics

– Wrapped burst lengths:

 8-bit data bus (DQ[7:0])

 Read-Write Data Strobe (RWDS)

– Bidirectional Data Strobe / Mask

– 16 bytes (8 clocks)

– Output at the start of all transactions to indicate refresh

latency

– 32 bytes (16 clocks)

– 64 bytes (32 clocks)

– Output during read transactions as Read Data Strobe

– Input during write transactions as Write Data Mask

– 128 bytes (64 clocks)

– Linear burst

– Hybrid option - one wrapped burst followed by linear burst

– Wrapped or linear burst type selected in each transaction

– Configurable output drive strength

 Package and Die Options

RESET#

CS#

DQ[7:0]

RWDS

– 24-ball FBGA footprint

CK#

Performance Summary

Read Transaction Timings

Maximum Current Consumption

Maximum Clock Rate at 1.8V V_CC/V_CC

Maximum Clock Rate at 3.0V V_CC/V_CC

166 MHz

100 MHz

36 ns

Burst Read or Write (linear burst at 166 MHz, 1.8V) 60 mA

Power On Reset

50 mA

300 µA

40 µA

Maximum Access Time, (t_ACCat 166 MHz)

Standby (CS# = High, 3V, 105 °C)

Deep Power Down (CS# = High, 3V, 105 °C)

Standby (CS# = High, 1.8V, 105 °C)

Deep Power Down (CS# = High, 1.8V, 105 °C)

Maximum CS# Access Time to first word at

166 MHz (excluding refresh latency)

56 ns

300 µA

20 µA

Errata: For information on silicon errata, see "Errata” on page 27. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 001-97964 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 01, 2016

12 3 4 5 6 7...29

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