Datasheet > 7KL0641DAHI02

7KL0641DAHI02

更新时间： 2022-02-26 13:05:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		动态存储器
页数	文件大小	规格书
29页	770K
描述
HyperRAMâ¢ Self-Refresh DRAM 3.0V/1.8V 64 Mb (8 MB)

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7KL0641DAHI02 数据手册

ADVANCE

S27KL0641, S27KS0641

4. Memory Space

When CA[46] is 0 a read or write transaction accesses the DRAM memory array.

Table 4.1 Memory Space Address Map

System Word Address

Unit Type

Count

CA Bits

Notes

Bits

Rows within 64 Mb

device

8192 (Rows)

A21 - A9

34 - 22

512 (word addresses)

1 kbytes

Row

1 (row)

A8 - A3

A2 - A0

21 - 16

2 - 0

Half-Page

8 (word addresses)

16 bytes

5. Register Space

When CA[46] is 1 a read or write transaction accesses the Register Space.

Table 5.1 Register Space Address Map

System

Address

—

31-27

44-40

26-19

39-32

00h

18-11

31-24

00h

10-3

23-16

00h

—

2-0

7-0

00h

CA Bits

15-8

00h

Identification Register 0

(read only)

C0h or E0h

Identification Register 1

(read only)

C0h or E0h

00h

01h

Configuration Register 0 Read

Configuration Register 0 Write

Configuration Register 1 Read

Configuration Register 1 Write

C0h or E0h

60h

00h

01h

00h

01h

C0h or E0h

60h

Note:

1. CA45 may be either 0 or 1 for either wrapped or linear read. CA45 must be 1 as only linear single word register writes are

supported.

5.1

Device Identification Registers

There are two read only, non-volatile, word registers, that provide information on the device selected when CS# is low. The device

information fields identify:



Manufacturer

Type

Density

– Row address bit count

– Column address bit count

Table 5.2 ID Register 0 Bit Assignments

Bits

15-14

Function

Reserved

Settings (Binary)

Reserved

0 - default

00000 - One Row address bit

...

12-8

Row Address Bit Count

11111 - Thirty-two row address bits

Document Number: 001-97964 Rev. *E

Page 7 of 29

1...4 5 678 9 10...29

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