ADVANCE
S27KL0641, S27KS0641
3. HyperBus Interface
For the general description of how the HyperBus interface operates in HyperRAM memories, refer to the HyperBus specification.
The following section describes HyperRAM device dependent aspects of HyperBus interface operation.
All bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low with CK = Low and
CK# = High. The transaction to be performed is presented to the HyperRAM device during the first three clock cycles in a DDR
manner using all six clock edges. These first three clocks transfer three words of Command / Address (CA0, CA1, CA2) information
to define the transaction characteristics:
Read or write transaction
Whether the transaction will be to the memory array or to register space.
Whether a read transaction will use a linear or wrapped burst sequence
The target half-page address (row and upper order column address)
The target Word (within half-page) address (lower order column address)
Once the transaction has been defined, a number of idle clock cycles are used to satisfy initial read or write access latency
requirements before data is transferred. During the Command-Address portion of all transactions, RWDS is used by the memory to
indicate whether additional initial access latency will be inserted for a required refresh of the memory array.
When data transfer begins, read data is edge aligned with RWDS transitions or write data is center aligned with clock transitions.
During read data transfer, RWDS serves as a source synchronous data timing strobe. During write data transfer, clock transitions
provide the data timing reference and RWDS is used as a data mask. When RWDS is Low during a write data transfer, the data byte
is written into memory; if RWDS is High during the transfer the byte is not written.
Data is transferred as 16-bit values with the first eight bits transferred on a High going CK (write data or CA bits) or RWDS edge
(read data) and the second eight bits being transferred on the Low going CK or RWDS edge. Data transfers during read or write
operations can be ended at any time by bringing CS# High when
CK = Low and CK# = High.
The clock may stop in the idle state while CS# is High.
The clock may also stop in the idle state for short periods while CS# is Low, as long as this does not cause a transaction to exceed
the CS# maximum time low (tCSM) limit. This is referred to as Active Clock Stop mode. In some HyperBus devices this mode is used
for power reduction. However, due to the relatively short tCSM period for completing each data transfer, the Active Clock Stop mode
is generally not useful for power reduction but, may be used for short duration data flow control by the HyperBus master.
3.1
Command-Address Bit Assignments
Table 3.1 Command-Address Bit Definitions
CA Bit#
Bit Name
Bit Function
Identifies the transaction as a read or write.
47
R/W#
R/W# = 1 indicates a Read transaction
R/W# = 0 indicates a Write transaction
Indicates whether the read or write transaction accesses the memory or register spaces.
AS = 0 indicates memory space.
AS = 1 indicates the register space.
Address Space
(AS)
46
45
The register space is used to access device ID and Configuration registers.
Indicates whether the burst will be linear or wrapped.
Burst Type = 0 indicates wrapped burst
Burst Type = 1 indicates linear burst
Burst Type
Reserved
Reserved for future row address expansion.
Reserved bits should be set to 0 by the HyperBus master.
44-35 (64 Mb)
34-22 (64 Mb)
21-16
Row Address Row component of the target address: System word address bits A23-A9.
Upper Column
Upper Column component of the target address: System word address bits A8-A3.
Address
Document Number: 001-97964 Rev. *E
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