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78M6618

更新时间: 2024-01-23 15:50:47
品牌 Logo 应用领域
矽力杰 - SILERGY /
页数 文件大小 规格书
32页 593K
描述
Octal Power and Energy Measurement IC

78M6618 技术参数

生命周期:Transferred包装说明:ROHS COMPLIANT, QFN-68
Reach Compliance Code:unknown风险等级:5.58
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-XQCC-N68
端子数量:68封装主体材料:UNSPECIFIED
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified表面贴装:YES
端子形式:NO LEAD端子位置:QUAD

78M6618 数据手册

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78M6618 Data Sheet  
1.6.1 SFR  
Several custom Special Function Registers (SFR) registers are implemented in the 78M6618’s 80515  
MPU. See the 78M6618 Programmer’s Reference Manual for more information regarding the mapping of  
functionality to specific SFR and IORAM addresses.  
1.7 XRAM  
The CE and MPU share a single, general purpose 4 KB RAM (also referred to as XRAM) for data. The  
XRAM is natively accessible as 32bit words from the CE and on 8 bit boundaries from the CPU. The  
XRAM is accessed by the CPU through addresses 0x0000 to 0x0FFF.  
1.8 IORAM  
The MPU accesses most of its external input and output functionality as well as programmable  
functionality through memory mapped IO (IORAM). The IORAM is accessed by the CPU as data  
addresses 0x2000 to 0x20FF. See the 78M6618 Programmer’s Reference Manual for more information  
regarding the mapping of functionality to specific IORAM addresses.  
1.9 FLASH  
The 78M6618 includes 128 KB of on-chip Flash memory. For read/write access from the CPU, the flash  
is broken into four 32 KB banks that are managed by SFR settings. For erasing of the flash memory from  
the CPU the flash is segmented into individual 1024-byte pages and also controlled by SFR settings. See  
the 78M6618 Programmer’s Reference Manual for more information regarding the use of flash and the  
mapping of functionality to specific SFR settings.  
1.9.1 Program Security  
The 78M6618 has functionality to guarantee the security of the user’s MPU and CE program code. When  
enabled, the security feature limits the ICE to global Flash erase operations only. All other ICE  
operations are blocked. Security is enabled by MPU code that is executed in a pre-boot interval before  
the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a  
global erase of the Flash, followed by a chip reset.  
1.10 Oscillator  
The 78M6618 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do  
not require a high-current oscillator circuit. The 78M6618 oscillator has been designed specifically to  
handle these crystals and is compatible with their high impedance and limited power handling capability.  
The oscillator is powered directly and only from the VBAT pin, which therefore must be connected to a  
DC voltage source not to exceed 4 V. The oscillator requires approximately 100 nA, which is negligible  
compared to the internal leakage of a battery  
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.  
1.11 PLL and Internal Clock Generation  
Timing for the device is derived from the 32.768 kHz crystal oscillator output. The PLL and on-chip timing  
functions provide several clocks which include:  
The MPU clock (CKMPU)  
The emulator clock (2 x CKMPU)  
The clock for the CE (CKCE)  
The delta-sigma ADC and FIR clock(CKADC, CKFIR)  
These internal clocks can be adjusted for various programmable rates which affect device functionality.  
See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability  
of the 78M6618 PLL and internal clock generation modules.  
Rev. 2  
9

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