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7700601EA

更新时间： 2024-11-07 21:54:11
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
13页 199K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

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中文翻译

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7700601EA 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.04Is Samacsys：N
其他特性：SISO OPERATION ALSO AVAILABLE计数方向：RIGHT
系列：LSJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：15 pF
逻辑集成电路类型：PARALLEL IN SERIAL OUT最大频率@ Nom-Sup：15000000 Hz
最大I（ol）：0.008 A位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：30 mA
Prop。Delay @ Nom-Sup：25 ns传播延迟（tpd）：25 ns
认证状态：Qualified施密特触发器：No
筛选级别：MIL-STD-883座面最大高度：5.08 mm
子类别：Shift Register最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.92 mm最小 fmax：25 MHz
Base Number Matches：1

7700601EA 数据手册

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SN54165, SN54LS165A, SN74165, SN74LS165A  
PARALLEL-LOAD 8-BIT SHIFT REGISTERS  
The SN54165 and SN74165 devices  
are obsolete and are no longer supplied.  
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002  
SN54165, SN54LS165A . . . J OR W PACKAGE  
SN74165 . . . N PACKAGE  
Complementary Outputs  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
SN74LS165A . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
Parallel-to-Serial Data Conversion  
SH/LD  
CLK  
E
V
CC  
CLK INH  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY POWER DISSIPATION  
TYPICAL  
TYPE  
’165  
D
C
B
A
26 MHz  
35 MHz  
210 mW  
90 mW  
F
G
H
’LS165A  
description  
Q
SER  
H
GND  
Q
H
The ’165 and ’LS165A are 8-bit serial shift  
registers that shift the data in the direction of Q  
A
toward Q when clocked. Parallel-in access to  
H
SN54LS165A . . . FK PACKAGE  
(TOP VIEW)  
each stage is made available by eight individual,  
direct data inputs that are enabled by a low level  
at the shift/load (SH/LD) input. These registers  
also feature gated clock (CLK) inputs and  
complementary outputs from the eighth bit. All  
inputs  
are  
diode-clamped  
to minimize  
3
2
1
20 19  
18  
transmission-line effects, thereby simplifying  
system design.  
4
5
6
7
8
D
C
NC  
B
A
E
F
NC  
G
17  
16  
15  
14  
Clocking is accomplished through a two-input  
positive-NOR gate, permitting one input to be  
used as a clock-inhibit function. Holding either of  
the clock inputs high inhibits clocking, and holding  
either clock input low with SH/LD high enables the  
other clock input. Clock inhibit (CLK INH) should  
be changed to the high level only while CLK is  
high. Parallel loading is inhibited as long asSH/LD  
is high. Data at the parallel inputs are loaded  
directly into the register while SH/LD is low,  
independently of the levels of CLK, CLK INH, or  
serial (SER) inputs.  
H
9 10 11 12 13  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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7700601EA 替代型号

型号 品牌 替代类型 描述 数据表
SN54LS165AJ TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SNJ54LS165AJ TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165AN TI

功能相似

 PARALLEL-LOAD 8-BIT SHIFT REGISTERS

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