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74LVCH162373ADGG,5

更新时间： 2024-11-12 14:49:07
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
18页 128K
描述
74LVC(H)162373A - 16-bit D-type transparent latch TSSOP 48-Pin

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74LVCH162373ADGG,5 技术参数

生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP,针数：48
Reach Compliance Code：compliant风险等级：5.16
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：6.8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

74LVCH162373ADGG,5 数据手册

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74LVC162373A; 74LVCH162373A  
16-bit D-type transparent latch; 30 series termination  
resistors; 5 V tolerant inputs/outputs; 3-state  
Rev. 4 — 14 May 2013  
Product data sheet  
1. General description  
The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with  
separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state  
outputs for bus-oriented applications. One latch enable (pin nLE) input and one output  
enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V  
devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow  
the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two  
sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is  
HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition,  
the latches are transparent, that is, the latch output changes each time its corresponding  
data inputs changes. When pin nLE is LOW, the latches store the information that was  
present at the data inputs a set-up time preceding the HIGH to LOW transition of pin  
nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs.  
When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the  
nOE input does not affect the state of the latches.  
The device is designed with 30 series termination resistors in both HIGH and LOW  
output stages to reduce line noise. Bus hold on data inputs eliminates the need for  
external pull-up resistors to hold unused inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pinout architecture  
Multiple low inductance supply pins for minimum noise and ground bounce  
Direct interface with TTL levels  
All data inputs have bus hold (74LVCH162373A only)  
High-impedance when VCC = 0 V  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
 
 
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