Datasheet > 74LVC2G86DP-Q100H

74LVC2G86DP-Q100H

更新时间： 2024-01-26 19:20:37

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管逻辑集成电路石英晶振
页数	文件大小	规格书
14页	109K
描述
74LVC2G86-Q100 - Dual 2-input EXCLUSIVE-OR gate TSSOP 8-Pin

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74LVC2G86DP-Q100H 技术参数

74LVC2G86-Q100

Dual 2-input EXCLUSIVE-OR gate

Rev. 1 — 7 May 2013

Product data sheet

1. General description

The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant inputs for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 24 mA output drive (V_CC= 3.0 V)

 CMOS low-power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

12 3 4 5 6 7...14

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