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74LVC2G08DP PDF预览

74LVC2G08DP

更新时间: 2024-02-23 23:41:30
品牌 Logo 应用领域
安世 - NEXPERIA PC光电二极管逻辑集成电路
页数 文件大小 规格书
20页 287K
描述
Dual 2-input AND gateProduction

74LVC2G08DP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP, TSSOP8,.16针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.39系列:LVC/LCX/Z
JESD-30 代码:S-PDSO-G8JESD-609代码:e4
长度:3 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.024 A
湿度敏感等级:1功能数量:2
输入次数:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.16封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.9 ns传播延迟(tpd):11.3 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

74LVC2G08DP 数据手册

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74LVC2G08  
Dual 2-input AND gate  
Rev. 18 — 23 January 2023  
Product data sheet  
1. General description  
The 74LVC2G08 is a dual 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices.  
This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant outputs for interfacing with 5 V logic  
Overvoltage tolerant inputs to 5.5 V  
IOFF circuitry provides partial Power-down mode operation  
High noise immunity  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power dissipation  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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