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74LVC1T45GW-Q100 PDF预览

74LVC1T45GW-Q100

更新时间: 2024-01-04 00:50:01
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
28页 349K
描述
Dual supply translating transceiver; 3-state

74LVC1T45GW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP,
针数:6Reach Compliance Code:compliant
风险等级:1.56系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6长度:2 mm
逻辑集成电路类型:BUS TRANSCEIVER湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):23.5 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

74LVC1T45GW-Q100 数据手册

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Nexperia  
74LVC1T45-Q100; 74LVCH1T45-Q100  
Dual supply translating transceiver; 3-state  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................2  
4. Marking..........................................................................2  
5. Functional diagram.......................................................2  
6. Pinning information......................................................3  
6.1. Pinning.........................................................................3  
6.2. Pin description.............................................................3  
7. Functional description................................................. 3  
8. Limiting values............................................................. 4  
9. Recommended operating conditions..........................4  
10. Static characteristics..................................................5  
11. Dynamic characteristics.............................................8  
11.1. Waveforms and test circuit.......................................13  
12. Typical propagation delay characteristics..............16  
13. Application information........................................... 22  
13.1. Unidirectional logic level-shifting application............22  
13.2. Bidirectional logic level-shifting application..............22  
13.3. Power-up considerations......................................... 23  
13.4. Enable times............................................................23  
14. Package outline........................................................ 24  
15. Abbreviations............................................................26  
16. Revision history........................................................26  
17. Legal information......................................................27  
© Nexperia B.V. 2019. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 19 March 2019  
©
74LVC_LVCH1T45_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 19 March 2019  
28 / 28  

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