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74LVC16245AEV,151 PDF预览

74LVC16245AEV,151

更新时间: 2024-11-25 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路
页数 文件大小 规格书
20页 228K
描述
74LVC16245A; 74LVCH16245A - 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state BGA 56-Pin

74LVC16245AEV,151 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:4.50 X 7 MM, 0.65 MM PITCH, PLASTIC, MO-225, SOT702-1, VFBGA-56
针数:56Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.25
Is Samacsys:N其他特性:WITH DIRECTION CONTROL
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PBGA-B56
JESD-609代码:e0长度:7 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:2
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA56,6X10,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法:TRAY
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
翻译:N/A宽度:4.5 mm
Base Number Matches:1

74LVC16245AEV,151 数据手册

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74LVC16245A; 74LVCH16245A  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Rev. 12 — 13 February 2012  
Product data sheet  
1. General description  
The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting  
3-state bus compatible outputs in both send and receive directions. The device features  
two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for  
direction control. nOE controls the outputs so that the buses are effectively isolated. This  
device can be used as two 8-bit transceivers or one 16-bit transceiver.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
High-impedance when VCC = 0 V  
All data inputs have bus hold (74LVCH16245A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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