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74LVC16373ADGG PDF预览

74LVC16373ADGG

更新时间： 2024-09-10 11:11:51
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 256K
描述
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction

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74LVC16373ADGG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSSOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.58
其他特性：IT ALSO OPERATES AT 1.65 TO 3.6V系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：14.4 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

74LVC16373ADGG 数据手册

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74LVC16373A; 74LVCH16373A  
16-bit D-type transparent latch with 5 V tolerant  
inputs/outputs; 3-state  
Rev. 10 — 1 October 2021  
Product data sheet  
1. General description  
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.  
The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The  
devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each  
controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the  
latches are transparent, a latch output will change each time its corresponding D-input changes.  
When nLE is LOW the latches store the information that was present at the inputs a set-up time  
preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.  
2. Features and benefits  
•
Overvoltage tolerant inputs to 5.5 V  
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power dissipation  
MULTIBYTE flow-through standard pinout architecture  
Multiple low inductance supply pins for minimum noise and ground bounce  
Direct interface with TTL levels  
All data inputs have bus hold (74LVCH16373A only)  
IOFF circuitry provides partial Power-down mode operation  
Complies with JEDEC standards:  
•
•
•
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
•
•
ESD protection:  
•
•
•
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 
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74LVC16373ADGG 替代型号

型号 品牌 替代类型 描述 数据表
IDT74LVCH16373APAG IDT

功能相似

 Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, GREEN, TSSOP-48
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 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX16373MTD FAIRCHILD

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 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

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