Datasheet > 74LVC138AD,112

74LVC138AD,112

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	167K
描述
74LVC138A - 3-to-8 line decoder/demultiplexer; inverting SOP 16-Pin

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74LVC138AD,112 数据手册

74LVC138A

NXP Semiconductors

3-to-8 line decoder/demultiplexer; inverting

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min Max

Min

Typ^[1]

Max

[4]

C_PD

power dissipation

capacitance

V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

9.9

15.8

21.1

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in V

N = number of inputs switching

(C_L V_CC² f_o) = sum of outputs

11. Waveforms

E1, E2

input

An, E3

input

GND

PLH

PHL

output

THL

TLH

mna374

THL

TLH

mna373

V_M= 1.5 V at V_CC 2.7 V;

V_M= 0.5  V_CCat V_CC< 2.7 V;

V_OLand V_OHare typical output voltage levels that occur

with the output load.

V_OLand V_OHare typical output voltage levels that occur

with the output load.

Fig 6. The inputs An, E3 to outputs Yn propagation

delays

Fig 7. The inputs En to outputs Yn propagation

delays

74LVC138A

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Product data sheet

Rev. 5 — 19 October 2011

7 of 16

1...4 5 678 9 10...16

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