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74LVC02APW-Q100J PDF预览

74LVC02APW-Q100J

更新时间: 2024-11-25 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
14页 164K
描述
74LVC02A-Q100 - Quad 2-input NOR gate TSSOP 14-Pin

74LVC02APW-Q100J 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
针数:14Reach Compliance Code:compliant
风险等级:5.78Base Number Matches:1

74LVC02APW-Q100J 数据手册

 浏览型号74LVC02APW-Q100J的Datasheet PDF文件第2页浏览型号74LVC02APW-Q100J的Datasheet PDF文件第3页浏览型号74LVC02APW-Q100J的Datasheet PDF文件第4页浏览型号74LVC02APW-Q100J的Datasheet PDF文件第5页浏览型号74LVC02APW-Q100J的Datasheet PDF文件第6页浏览型号74LVC02APW-Q100J的Datasheet PDF文件第7页 
74LVC02A-Q100  
Quad 2-input NOR gate  
Rev. 1 — 4 April 2013  
Product data sheet  
1. General description  
The 74LVC02A-Q100 provides four 2-input NOR gates.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V applications.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
5 V tolerant inputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
 
 

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