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74LV574 PDF预览

74LV574

更新时间： 2024-01-16 21:00:05
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
12页 125K
描述
Octal D-type flip-flop; positive edge-trigger 3-State

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74LV574 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP20,.25Reach Compliance Code：unknown
风险等级：5.73Is Samacsys：N
JESD-30 代码：R-PDSO-G20负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：20000000 Hz
最大I（ol）：0.008 A功能数量：8
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：25 ns
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
Base Number Matches：1

74LV574 数据手册

 浏览型号74LV574的Datasheet PDF文件第1页浏览型号74LV574的Datasheet PDF文件第3页浏览型号74LV574的Datasheet PDF文件第4页浏览型号74LV574的Datasheet PDF文件第5页浏览型号74LV574的Datasheet PDF文件第6页浏览型号74LV574的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Octal D-type flip-flop; positive edge-trigger (3-State)  
74LV574  
FEATURES  
• Wide operating voltage: 1.0 to 5.5V  
• Optimized for Low Voltage applications: 1.0 to 3.6V  
DESCRIPTION  
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and  
function compatible with 74HC/HCT574.  
The 74LV574 is an octal D-type flip–flop featuring separate D-type  
inputs for each flip-flop and non-inverting 3-state outputs for bus  
oriented applications. A clock (CP) and an output enable (OE) input  
are common to all flip-flops.  
• Accepts TTL input levels between V = 2.7V and V = 3.6V  
CC  
CC  
• Typical V  
(output ground bounce) t 0.8V at V = 3.3V,  
OLP  
CC  
T
= 25°C  
amb  
The eight flip-flops will store the state of their individual D-inputs that  
meet the set-up and hold times requirements on the LOW-to-HIGH  
CP transition.  
• Typical V  
(output V undershoot) u 2V at V = 3.3V,  
OHV  
OH  
CC  
T
= 25°C  
amb  
• Common 3-State output enable input  
• Output capability: bus driver  
When OE is LOW, the contents of the eight flip-flops is available at  
the outputs. When OE is HIGH, the outputs go to the high  
impedance OFF-state. Operation of the OE input does not affect the  
state of the flip-flops.  
• I category: MSI  
CC  
QUICK REFERENCE DATA  
GND = 0V; T  
= 25°C; t =t v2.5 ns  
amb  
r f  
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
C = 15pF  
L
Propagation delay  
CP to Q  
V
CC  
= 3.3V  
t
f
/t  
13  
ns  
PHL PLH  
n
Maximum clock frequency  
Input capacitance  
C = 15pF, V = 3.3V  
77  
3.5  
25  
MHz  
pF  
max  
L
CC  
C
C
I
Power dissipation capacitance per flip-flop  
Notes 1 and 2  
pF  
PD  
NOTES:  
1. C is used to determine the dynamic power dissipation (P in µW)  
PD  
D
2
2
P
= C   V  
x f )S (C   V  
  f ) where:  
D
PD  
CC  
i
L
CC o  
f = input frequency in MHz; C = output load capacity in pF;  
i
L
f = output frequency in MHz; V = supply voltage in V;  
o
CC  
2
S (C   V  
  f ) = sum of the outputs.  
L
CC  
o
2. The condition is V = GND to V  
I
CC  
ORDERING AND PACKAGE INFORMATION  
OUTSIDE NORTH  
AMERICA  
PACKAGES  
TEMPERATURE RANGE  
NORTH AMERICA  
PKG. DWG. #  
20-Pin Plastic DIL  
–40°C to +125°C  
–40°C to +125°C  
–40°C to +125°C  
–40°C to +125°C  
74LV574 N  
74LV574 D  
74LV574 N  
74LV574 D  
SOT146-1  
SOT163-1  
SOT339-1  
SOT360-1  
20-Pin Plastic SO  
20-Pin Plastic SSOP Type II  
20-Pin Plastic TSSOP Type I  
74LV574 DB  
74LV574 PW  
74LV574 DB  
74LV574PW DH  
PIN DESCRIPTION  
FUNCTION TABLE  
PIN NUMBER SYMBOL  
FUNCTION  
INPUTS  
OUTPUTS  
Q0 to Q7  
OPERATING  
MODES  
INTERNAL  
FLIP-FLOPS  
1
OE  
Output enabled input (active LOW)  
OE CP Dn  
2, 3, 4, 5,  
6, 7, 8, 9  
Load and read  
register  
L
L
↑
↑
l
h
L
H
L
H
D0–D7  
Data inputs  
19, 18, 17, 16,  
15, 14, 13, 12  
Load register and  
disable outputs  
H
H
↑
↑
l
h
L
H
Z
Z
Q0–Q7  
GND  
CP  
3-State flip-flop outputs  
Ground (0V)  
10  
11  
20  
H
h
=
=
HIGH voltage level  
HIGH voltage level one set-up time prior to the  
LOW-to-HIGH CP transition  
Clock input (LOW-to-HIGH,  
edge-triggered)  
L
l
=
=
LOW voltage level  
LOW voltage level one set-up time prior to the  
LOW-to-HIGH CP transition  
VCC  
Positive supply voltage  
Z
↑
=
=
High impedance OFF-state  
LOW–to–HIGH clock transition  
2
1998 Jun 10  
853-1990 19545  
1234567...12

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