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74LV241D,112 PDF预览

74LV241D,112

更新时间: 2024-11-12 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 105K
描述
74LV241 - Octal buffer/line driver; 3-state SOP 20-Pin

74LV241D,112 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOP包装说明:7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.74
Is Samacsys:N其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION
控制类型:ENABLE LOW/HIGH系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:21 ns
传播延迟(tpd):36 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74LV241D,112 数据手册

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74LV241  
Octal buffer/line driver; 3-state  
Rev. 03 — 10 October 2005  
Product data sheet  
1. General description  
The 74LV241 is a low-voltage, Si-gate CMOS device and is pin and function compatible  
with 74HC241 and 74HCT241.  
The 74LV241 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state  
outputs are controlled by the output enable inputs (pins 1OE and 2OE).  
2. Features  
Optimized for low-voltage applications from 1.0 V to 3.6 V  
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V and Tamb = 25 °C  
ESD protection:  
HBM EIA/JESD22-A114-C exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.  
Symbol Parameter  
Conditions  
CL = 15 pF;  
CC = 3.3 V  
Min  
Typ  
Max  
Unit  
tPHL, tPLH propagation delay  
1An to 1Yn, 2An to 2Yn  
-
8.0  
-
ns  
V
Ci  
input capacitance  
-
-
3.5  
30  
-
-
pF  
pF  
[1]  
CPD  
power dissipation  
capacitance  
VCC = 3.3 V;  
VI = GND to VCC  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
 
 
 
 

74LV241D,112 替代型号

型号 品牌 替代类型 描述 数据表
74LV241DB,112 NXP

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74LV241 - Octal buffer/line driver; 3-state SSOP2 20-Pin

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