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74LS83ADCQR PDF预览

74LS83ADCQR

更新时间: 2024-11-07 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
5页 55K
描述
Adder/Subtractor, TTL, CDIP16,

74LS83ADCQR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:compliant
风险等级:5.65JESD-30 代码:R-XDIP-T16
JESD-609代码:e0逻辑集成电路类型:ADDER/SUBTRACTOR
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V子类别:Arithmetic Circuits
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

74LS83ADCQR 数据手册

 浏览型号74LS83ADCQR的Datasheet PDF文件第2页浏览型号74LS83ADCQR的Datasheet PDF文件第3页浏览型号74LS83ADCQR的Datasheet PDF文件第4页浏览型号74LS83ADCQR的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS83A  
4-Bit Binary Adder with Fast Carry  
General Description  
Features  
These full adders perform the addition of two 4-bit binary  
numbers. The sum () outputs are provided for each bit  
and the resultant carry (C4) is obtained from the fourth bit.  
These adders feature full internal look ahead across all four  
bits. This provides the system designer with partial look-  
ahead performance at the economy and reduced package  
count of a ripple-carry implementation.  
Full-carry look-ahead across the four bits  
Systems achieve partial look-ahead performance with  
the economy of ripple carry  
Typical add times  
Two 8-bit words 25 ns  
Two 16-bit words 45 ns  
Typical power dissipation per 4-bit adder 95 mW  
The adder logic, including the carry, is implemented in its  
true form meaning that the end-around carry can be  
accomplished without the need for logic or level inversion.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS83AN  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006378  
www.fairchildsemi.com  

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