5秒后页面跳转
74LS51 PDF预览

74LS51

更新时间: 2024-11-08 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 50K
描述
Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate

74LS51 数据手册

 浏览型号74LS51的Datasheet PDF文件第2页浏览型号74LS51的Datasheet PDF文件第3页浏览型号74LS51的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS51  
Dual 2-Wide 2-Input, 2-Wide 3-Input  
AND-OR-INVERT Gate  
General Description  
This device contains two independent combinations of  
gates each of which performs the logic AND-OR-INVERT  
function. Each package contains one 2-wide 2-input and  
one 2-wide 3-input AND-OR-INVERT gates.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS51M  
DM74LS51N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y1 = (A1) (B1) (C1) + (D1) (E1) (F1)  
Inputs  
Output  
A1  
H
B1  
H
C1  
H
D1  
X
E1  
X
F1  
X
Y1  
L
X
X
X
H
H
H
L
Other Combinations  
H
Y2 = ((A2) (B2) + (C2) (D2))  
Inputs  
Output  
A2  
B2  
H
C2  
X
D2  
X
Y2  
L
H
X
X
H
H
L
Other combinations  
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006369  
www.fairchildsemi.com  

与74LS51相关器件

型号 品牌 获取价格 描述 数据表
74LS51A NXP

获取价格

AND-OR-Invert Gate, LS Series, 2-Func, 6-Input, TTL, PDIP14
74LS51DC FAIRCHILD

获取价格

AND-OR-Invert Gate, TTL, CDIP14,
74LS51DCQM ROCHESTER

获取价格

AND-OR-Invert Gate
74LS51DCQR ROCHESTER

获取价格

AND-OR-Invert Gate
74LS51DCQR FAIRCHILD

获取价格

AND-OR-Invert Gate, TTL, CDIP14,
74LS51F NXP

获取价格

AND-OR-Invert Gate, LS Series, 2-Func, 6-Input, TTL, CDIP14
74LS51FCQM FAIRCHILD

获取价格

AND-OR-Invert Gate, TTL, CDFP14,
74LS51PC ETC

获取价格

2/2-input and 3/3-input AND-NOR Gate
74LS51PCQM FAIRCHILD

获取价格

AND-OR-Invert Gate, TTL, PDIP14,
74LS51PCQR FAIRCHILD

获取价格

AND-OR-Invert Gate, TTL, PDIP14,