Datasheet > 74LS293

74LS293

更新时间： 2024-11-17 22:53:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
7页	207K
描述
DECADE COUNTER; 4-BIT BINARY COUNTER

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数据手册

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74LS293 数据手册

SN54/74LS290

SN54/74LS293

DECADE COUNTER;

4-BIT BINARY COUNTER

The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit ripple type

counters partitioned into two sections. Each counter has a divide-by-two sec-

tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section

which are triggered by a HIGH-to-LOW transition on the clock inputs. Each

section can be used separately or tied together (Q to CP)to form BCD,

Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated

Master Reset (Clear), and the LS290 also has a 2-input gated Master Set

(Preset 9).

DECADE COUNTER;

4-BIT BINARY COUNTER

LOW POWER SCHOTTKY

• Corner Power Pin Versions of the LS90 and LS93

• Low Power Consumption . . . Typically 45 mW

• High Count Rates . . . Typically 42 MHz

• Choice of Counting Modes . . . BCD, Bi-Quinary, Binary

• Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX

CERAMIC

CASE 632-08

CONNECTION DIAGRAM DIP (TOP VIEW)

N SUFFIX

PLASTIC

CASE 646-06

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

LS290

D SUFFIX

SOIC

CASE 751A-02

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

LS293

PIN NAMES

LOADING (Note a)

HIGH

LOW

1.5 U.L.

2.0 U.L.

1.0 U.L.

0.25 U.L.

5 (2.5) U.L.

CP1

MR1, MR2

MS1, MS2

Clock (Active LOW going edge) Input to ÷2 Section.

Clock (Active LOW going edge) Input to ÷5 Section (LS290).

Clock (Active LOW going edge) Input to ÷8 Section (LS293).

Master Reset (Clear) Inputs

Master Set (Preset-9, LS290) Inputs

Output from ÷2 Section (Notes b & c)

0.05 U.L.

0.5 U.L.

10 U.L.

Q1, Q2, Q3

Outputs from ÷5 & ÷8 Sections (Note b)

10 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

c) The Q Outputs are guaranteed to drive the full fan-out plus the CP Input of the device.

FAST AND LS TTL DATA

5-466

12 3 4 5 6 7

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与74LS293相关器件

型号	品牌	获取价格	描述	数据表
74LS293A	NXP	获取价格	IC LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14, Counter
74LS293DCQM	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, CDIP14,
74LS293DCQR	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, CDIP14,
74LS293FCQR	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, CDFP14,
74LS293N	ROCHESTER	获取价格	Decade Counter,
74LS293PC	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, PDIP14,
74LS293PCQM	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, PDIP14,
74LS293SC	FAIRCHILD	获取价格	Binary Counter, Asynchronous, Up Direction, TTL, PDSO14,
74LS294	TI	获取价格	PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
74LS295	TI	获取价格	4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-STATE OUTPUTS