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74LS298 PDF预览

74LS298

更新时间: 2024-11-20 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 复用器存储
页数 文件大小 规格书
4页 47K
描述
Quad 2-Port Register Multiplexer with Storage

74LS298 数据手册

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October 1988  
Revised March 2000  
DM74LS298  
Quad 2-Port Register Multiplexer with Storage  
General Description  
Features  
Select from two data sources  
Fully edge-triggered operation  
Typical power dissipation of 65 mW  
The DM74LS298 is a quad 2-port register. It is the logical  
equivalent of a quad 2-input multiplexer followed by a quad  
4-bit edge-triggered register.  
A Common Select input  
selects between two 4-bit input ports (data sources). The  
selected data is transferred to the output register synchro-  
nous with the HIGH-to-LOW transition of the Clock input.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS298N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Logic Symbol  
Connection Diagram  
V
= Pin 16  
CC  
GND = Pin 8  
Pin Descriptions  
Truth Table  
Pin Names  
Description  
Common Select Inputs  
Inputs  
I0x  
Output  
S
I1x  
Qx  
S
CP  
Clock Pulse Input (Active Falling Edge)  
Source 0 Data Inputs  
l
l
X
X
l
L
H
L
I0a, I0d  
I1a, I1d  
Qa, Qd  
l
h
X
X
Source 1 Data Inputs  
h
h
Flip-Flip Outputs  
h
H
l = LOW Voltage Level one setup time prior to the HIGH-to-LOW clock  
transition.  
h = HIGH Voltage Level one setup time prior to the HIGH-to-LOW clock  
transition.  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
© 2000 Fairchild Semiconductor Corporation  
DS009826  
www.fairchildsemi.com  

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