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74LS221N PDF预览

74LS221N

更新时间： 2024-02-15 22:18:52
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管时钟
页数 文件大小 规格书
8页 124K
描述
LOW POWER SCHOTTKY

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中文翻译

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74LS221N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP-16Reach Compliance Code：unknown
风险等级：5.91Is Samacsys：N
系列：LSJESD-30 代码：R-PDIP-T16
JESD-609代码：e0逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：70 °C
最低工作温度：输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
传播延迟（tpd）：80 ns认证状态：Not Qualified
子类别：Prescaler/Multivibrators最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

74LS221N 数据手册

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Each multivibrator of the LS221 features a negative-transition-  
triggered input and a positive-transition-triggered input either of  
which can be used as an inhibit input.  
http://onsemi.com  
Pulse triggering occurs at a voltage level and is not related to the  
transition time of the input pulse. Schmitt-trigger input circuitry for B  
input allows jitter-free triggering for inputs as slow as 1 volt/second,  
providing the circuit with excellent noise immunity. A high immunity  
LOW  
POWER  
SCHOTTKY  
to V noise is also provided by internal latching circuitry.  
CC  
Once triggered, the outputs are independent of further transitions of  
the inputs and are a function of the timing components. The output  
pulses can be terminated by the overriding clear. Input pulse width  
may be of any duration relative to the output pulse width. Output pulse  
width may be varied from 35 nanoseconds to a maximum of 70 s by  
choosing appropriate timing components. With R = 2.0 kΩ and C  
= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise  
and fall times are independent of pulse length.  
ext  
ext  
16  
1
Pulse width stability is achieved through internal compensation and  
PLASTIC  
N SUFFIX  
CASE 648  
is virtually independent of V and temperature. In most applications,  
CC  
pulse stability will only be limited by the accuracy of external timing  
components.  
Jitter-free operation is maintained over the full temperature and V  
CC  
ranges for greater than six decades of timing capacitance (10 pF to 10  
µF), and greater than one decade of timing resistance (2.0 to 100 kΩ  
for the SN74LS221). Pulse width is defined by the relationship:  
16  
1
t (out) = C  
R
ln 2.0 ≈ 0.7 C  
R ; where t is in ns if C is in  
ext ext W ext  
w
ext ext  
pF and R is in kΩ. If pulse cutoff is not critical, capacitance up to  
ext  
SOIC  
D SUFFIX  
CASE 751B  
1000 µF and resistance as low as 1.4 kΩ may be used. The range of  
jitter-free pulse widths is extended if V  
temperature.  
is 5.0 V and 25°C  
CC  
• SN74LS221 is a Dual Highly Stable One-Shot  
• Overriding Clear Terminates Output Pulse  
• Pin Out is Identical to SN74LS123  
ORDERING INFORMATION  
GUARANTEED OPERATING RANGES  
Device  
Package  
16 Pin DIP  
16 Pin  
Shipping  
Symbol  
Parameter  
Supply Voltage  
Min  
4.75  
0
Typ  
5.0  
25  
Max  
5.25  
70  
Unit  
V
SN74LS221N  
SN74LS221D  
2000 Units/Box  
V
CC  
2500/Tape & Reel  
T
A
Operating Ambient  
Temperature Range  
°C  
I
Output Current – High  
Output Current – Low  
–0.4  
8.0  
mA  
mA  
OH  
I
OL  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
December, 1999 – Rev. 6  
SN74LS221/D  
12345678

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