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74LS241 PDF预览

74LS241

更新时间: 2024-11-17 22:53:15
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页数 文件大小 规格书
6页 145K
描述
Octal TRI-STATE Buffers/Line Drivers/Line Receivers

74LS241 数据手册

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April 1992  
DM54LS240/DM74LS240,  
DM54LS241/DM74LS241  
Octal TRI-STATE Buffers/Line Drivers/Line Receivers  
Y
É
Typical I (sink current)  
OL  
General Description  
54LS  
74LS  
12 mA  
24 mA  
These buffers/line drivers are designed to improve both the  
performance and PC board density of TRI-STATE buffers/  
drivers employed as memory-address drivers, clock drivers,  
and bus-oriented transmitters/receivers. Featuring 400 mV  
of hysteresis at each low current PNP data line input, they  
provide improved noise rejection and high fanout outputs  
and can be used to drive terminated lines down to 133X.  
Y
Y
Typical I  
54LS  
74LS  
(source current)  
OH  
b
b
12 mA  
15 mA  
Typical propagation delay times  
Inverting 10.5 ns  
Noninverting 12 ns  
Y
Y
Typical enable/disable time 18 ns  
Typical power dissipation (enabled)  
Features  
Y
TRI-STATE outputs drive bus lines directly  
Inverting 130 mW  
Noninverting 135 mW  
Y
PNP inputs reduce DC loading on bus lines  
Y
Hysteresis at data inputs improves noise margins  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/6411–1  
TL/F/6411–2  
Order Number DM54LS240J,  
DM54LS240W, DM54LS240E,  
DM74LS240WM or DM74LS240N  
See NS Package Number E20A, J20A,  
M20B, N20A or W20A  
Order Number DM54LS241J,  
DM54LS241W, DM54LS241E,  
DM74LS241WM or DM74LS241N  
See NS Package Number E20A, J20A,  
M20B, N20A or W20A  
Function Tables  
LS240  
LS241  
G
Inputs  
Output  
Y
Inputs  
1A  
Outputs  
G
A
G
2A  
1Y  
2Y  
L
L
L
H
X
H
L
X
X
X
H
H
L
L
L
L
H
X
X
X
X
X
X
X
L
L
H
Z
H
Z
H
X
X
X
L
H
Z
H
X
e
e
e
e
L
Low Logic Level  
High Logic Level  
H
X
Z
Either Low or High Logic Level  
High Impedance  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6411  
RRD-B30M105/Printed in U. S. A.  

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