Datasheet > 74LS221

74LS221

更新时间： 2024-02-04 19:06:30

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	111K
描述
Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

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74LS221 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP-16	Reach Compliance Code：	unknown
风险等级：	5.91	Is Samacsys：	N
系列：	LS	JESD-30 代码：	R-PDIP-T16
JESD-609代码：	e0	逻辑集成电路类型：	MONOSTABLE MULTIVIBRATOR
数据/时钟输入次数：	2	功能数量：	2
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
传播延迟（tpd）：	80 ns	认证状态：	Not Qualified
子类别：	Prescaler/Multivibrators	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

74LS221 数据手册

August 1986

Revised April 2000

DM74LS221 Dual Non-Retriggerable One-Shot

with Clear and Complementary Outputs

General Description

Features

The DM74LS221 is a dual monostable multivibrator with

Schmitt-trigger input. Each device has three inputs permit-

ting the choice of either leading-edge or trailing-edge trig-

gering. Pin (A) is an active-LOW trigger transition input and

pin (B) is an active-HIGH transition Schmitt-trigger input

that allows jitter free triggering for inputs with transition

rates as slow as 1 volt/second. This provides the input with

excellent noise immunity. Additionally an internal latching

circuit at the input stage also provides a high immunity to

■ A dual, highly stable one-shot

■ Compensated for V_CCand temperature variations

■ Pin-out identical to DM74LS123 (Note 1)

■ Output pulse width range from 30 ns to 70 seconds

■ Hysteresis provided at (B) input for added noise

immunity

■ Direct reset terminates output pulse

■ Triggerable from CLEAR input

■ DTL, TTL compatible

V_CCnoise. The clear (CLR) input can terminate the output

pulse at a predetermined time independent of the timing

components. This (CLR) input also serves as a trigger

input when it is pulsed with a low level pulse transition

■ Input clamp diodes

(

). To obtain the best and trouble free operation from

this device please read operating rules as well as the Fair-

child Semiconductor one-shot application notes carefully

and observe recommendations.

Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;

refer to Operating Rules #10 in this datasheet.

Ordering Code:

Order Number Package Number

Package Description

DM74LS221M

DM74LS221SJ

DM74LS221N

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLEAR

↑

↓

↑ (Note 2)

H = HIGH Logic Level

L = LOW Logic Level

X = Can Be Either LOW or HIGH

↑ = Positive Going Transition

↓ = Negative Going Transition

= A Positive Pulse

= A Negative Pulse

Note 2: This mode of triggering requires first the B input be set from a

LOW-to-HIGH level while the CLEAR input is maintained at logic LOW

level. Then with the B input at logic HIGH level, the CLEAR input whose

positive transition from LOW-to-HIGH will trigger an output pulse.

DS006409

www.fairchildsemi.com

12 3 4 5 6 7 8

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与74LS221相关器件

型号	品牌	获取价格	描述	数据表
74LS221B	NXP	获取价格	IC MONOSTABLE MULTIVIBRATOR, PDIP16, Prescaler/Multivibrator
74LS221N	MOTOROLA	获取价格	DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
74LS221N	ONSEMI	获取价格	LOW POWER SCHOTTKY
74LS22D	TI	获取价格	LS SERIES, DUAL 4-INPUT NAND GATE, PDSO14
74LS22DC	FAIRCHILD	获取价格	NAND Gate, TTL, CDIP14,
74LS22DCQM	FAIRCHILD	获取价格	NAND Gate, TTL, CDIP14,
74LS22DCQR	FAIRCHILD	获取价格	NAND Gate, TTL, CDIP14,
74LS22DR	TI	获取价格	LS SERIES, DUAL 4-INPUT NAND GATE, PDSO14
74LS22FCQR	FAIRCHILD	获取价格	NAND Gate, TTL, CDFP14,
74LS22J	TI	获取价格	暂无描述

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