Datasheet > 74LS112

74LS112

更新时间： 2024-11-11 22:53:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
4页	150K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

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数据手册

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74LS112 数据手册

SN54/74LS112A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and

asynchronous set and clear inputs to each flip-flop. When the clock goes

HIGH, the inputs are enabled and data will be accepted. The logic level of the

J and K inputs may be allowed to change when the clock pulse is HIGH and

thebistablewillperformaccordingtothetruthtableaslongasminimumset-up

and hold time are observed. Input data is transferred to the outputs on the

negative-going edge of the clock pulse.

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

D SUFFIX

SOIC

CASE 751B-03

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

MODE SELECT — TRUTH TABLE

INPUTS

OUTPUTS

OPERATING MODE

Set

LOGIC SYMBOL

Reset (Clear)

*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

* BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates

are unpredictable if S and C go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

l, h (q) = one set-up time prior to the HIGH to LOW clock transition.

FAST AND LS TTL DATA

5-185

12 3 4

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与74LS112相关器件

型号	品牌	获取价格	描述	数据表
74LS112B	NXP	获取价格	J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TT
74LS112DC	ETC	获取价格	J-K-Type Flip-Flop
74LS112DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP16,
74LS112F	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CE
74LS112N	RAYTHEON	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP16,
74LS112PC	ETC	获取价格	J-K-Type Flip-Flop
74LS112PCQR	FAIRCHILD	获取价格	暂无描述
74LS113A	NXP	获取价格	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
74LS113AD	ROCHESTER	获取价格	J-K Flip-Flop
74LS113DCQR	FAIRCHILD	获取价格	Jbar-Kbar Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP14,