74LS112

更新时间： 2024-11-11 22:53:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
5页	55K
描述
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

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数据手册

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74LS112 数据手册

August 1986

Revised March 2000

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

falling edge of the clock pulse. Data on the J and K inputs

may be changed while the clock is HIGH or LOW without

affecting the outputs as long as the setup and hold times

are not violated. A low logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic

levels of the other inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74KS112AM

DM74LS112AN

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

PR CLR CLK

↓

H (Note 1) H (Note 1)

Q₀

↓

Toggle

Q₀

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

↓ = Negative Going Edge of Pulse

= The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each falling edge of the clock pulse.

Note 1: This configuration is nonstable; that is, it will not persist when

preset and/or clear inputs return to their inactive (HIGH) level.

DS006382

www.fairchildsemi.com

12 3 4 5

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与74LS112相关器件

型号	品牌	获取价格	描述	数据表
74LS112B	NXP	获取价格	J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TT
74LS112DC	ETC	获取价格	J-K-Type Flip-Flop
74LS112DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP16,
74LS112F	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CE
74LS112N	RAYTHEON	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP16,
74LS112PC	ETC	获取价格	J-K-Type Flip-Flop
74LS112PCQR	FAIRCHILD	获取价格	暂无描述
74LS113A	NXP	获取价格	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
74LS113AD	ROCHESTER	获取价格	J-K Flip-Flop
74LS113DCQR	FAIRCHILD	获取价格	Jbar-Kbar Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP14,