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74LCX38MTC_NL PDF预览

74LCX38MTC_NL

更新时间: 2024-11-17 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
7页 124K
描述
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74LCX38MTC_NL 数据手册

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October 1995  
Revised February 2005  
74LCX38  
Low Voltage Quad 2-Input NAND Gate (Open Drain)  
with 5V Tolerant Inputs  
General Description  
The LCX38 contains four 2-input open drain NAND gates.  
The inputs tolerate voltages up to 7V allowing the interface  
of 5V systems to 3V systems.  
Features  
5V tolerant inputs  
2.3V to 3.6V VCC specifications provided  
5.0 ns tPD max (VCC 3.3V), 10 A ICC max  
The 74LCX38 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Power down high impedance inputs and outputs  
24 mA output drive (VCC 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model 2000V  
Machine model 150V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX38M  
M14A  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74LCX38MX_NL  
(Note 1)  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74LCX38SJ  
M14D  
MTC14  
MTC14  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX38MTC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX38MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
On  
Description  
Inputs  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS012574  
www.fairchildsemi.com  

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