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74HCT564D PDF预览

74HCT564D

更新时间: 2024-02-15 00:18:19
品牌 Logo 应用领域
恩智浦 - NXP 触发器逻辑集成电路
页数 文件大小 规格书
7页 62K
描述
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74HCT564D 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.54其他特性:BROADSIDE VERSION OF 534
系列:HCTJESD-30 代码:R-PDIP-T20
长度:26.73 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):53 ns
认证状态:Not Qualified座面最大高度:4.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

74HCT564D 数据手册

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Philips Semiconductors  
Product specification  
Octal D-type flip-flop; positive-edge trigger;  
3-state; inverting  
74HC/HCT564  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: bus driver  
ICC category: MSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
OE  
D0 to D7  
CP  
0.80  
0.25  
1.00  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
VCC  
+25  
40 to +85 40 to +125  
WAVEFORMS  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
CP to Qn  
19  
19  
19  
5
35  
35  
30  
12  
44  
44  
38  
15  
53  
53  
45  
18  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.5 Fig.6  
4.5 Fig.8  
4.5 Fig.8  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.7  
tPZH/ tPZL 3-state output enable  
time OE to Qn  
t
PHZ/ tPLZ 3-state output disable  
time OE to Qn  
tTHL/ tTLH output transition time  
tW  
clock pulse width  
HIGH or LOW  
18  
12  
3
8
23  
15  
3
27  
18  
3
tsu  
th  
set-up time  
Dn to CP  
3
hold time  
Dn to CP  
2  
56  
fmax  
maximum clock pulse  
frequency  
27  
22  
18  
MHz 4.5 Fig.6  
December 1990  
6

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