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74HCT4060D-T PDF预览

74HCT4060D-T

更新时间: 2024-11-24 19:29:27
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
25页 131K
描述
IC HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT-109, SOP-16, Counter

74HCT4060D-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证:符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.05Is Samacsys:N
其他特性:BUILT-IN OSCILLATOR计数方向:UP
系列:HCTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):99 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Counters
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:20 MHz
Base Number Matches:1

74HCT4060D-T 数据手册

 浏览型号74HCT4060D-T的Datasheet PDF文件第2页浏览型号74HCT4060D-T的Datasheet PDF文件第3页浏览型号74HCT4060D-T的Datasheet PDF文件第4页浏览型号74HCT4060D-T的Datasheet PDF文件第5页浏览型号74HCT4060D-T的Datasheet PDF文件第6页浏览型号74HCT4060D-T的Datasheet PDF文件第7页 
74HC4060; 74HCT4060  
14-stage binary ripple counter with oscillator  
Rev. 03 — 14 July 2008  
Product data sheet  
1. General description  
The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible  
with the HEF4060.  
The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators  
with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and  
Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator  
configuration allows design of either RC or crystal oscillator circuits. The oscillator may be  
replaced by an external clock signal at input RS. In this case keep the other oscillator pins  
(RTC and CTC) floating. The counter advances on the negative-going transition of RS. A  
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of  
other input conditions. In the HCT version, the MR input is TTL compatible, but the RS  
input has CMOS input switching levels and can be driven by a TTL output by using a  
pull-up resistor to VCC  
.
2. Features  
I All active components on chip  
I RC or crystal oscillator configuration  
I Complies with JEDEC standard no. 7 A  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
I Control counters  
I Timers  
I Frequency dividers  
I Time-delay circuits  
 
 
 

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