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74HCT4053N,112 PDF预览

74HCT4053N,112

更新时间: 2024-11-20 14:48:55
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
32页 248K
描述
74HC(T)4053 - Triple 2-channel analog multiplexer/demultiplexer DIP 16-Pin

74HCT4053N,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXERJESD-30 代码:R-PDIP-T16
JESD-609代码:e4标称负供电电压 (Vsup):
信道数量:1功能数量:3
端子数量:16标称断态隔离度:50 dB
通态电阻匹配规范:9 Ω最大通态电阻 (Ron):180 Ω
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):260
电源:5,GND/-5 V认证状态:Not Qualified
最大信号电流:0.025 A子类别:Multiplexer or Switches
最大供电电流 (Isup):0.16 mA标称供电电压 (Vsup):4.5 V
表面贴装:NO最长断开时间:44 ns
最长接通时间:48 ns切换:BREAK-BEFORE-MAKE
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

74HCT4053N,112 数据手册

 浏览型号74HCT4053N,112的Datasheet PDF文件第2页浏览型号74HCT4053N,112的Datasheet PDF文件第3页浏览型号74HCT4053N,112的Datasheet PDF文件第4页浏览型号74HCT4053N,112的Datasheet PDF文件第5页浏览型号74HCT4053N,112的Datasheet PDF文件第6页浏览型号74HCT4053N,112的Datasheet PDF文件第7页 
74HC4053; 74HCT4053  
Triple 2-channel analog multiplexer/demultiplexer  
Rev. 8 — 19 July 2012  
Product data sheet  
1. General description  
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible  
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a  
common enable input (E). Each multiplexer/demultiplexer has two independent  
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select  
inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state)  
by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent  
of S1 to S3.  
VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).  
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for  
74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as  
a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.  
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically  
ground).  
2. Features and benefits  
Wide analog input voltage range from 5 V to +5 V  
Low ON resistance:  
80 (typical) at VCC VEE = 4.5 V  
70 (typical) at VCC VEE = 6.0 V  
60 (typical) at VCC VEE = 9.0 V  
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals  
Typical ‘break before make’ built-in  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

74HCT4053N,112 替代型号

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