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74HCT4053D

更新时间： 2024-01-02 00:21:20
品牌 Logo 应用领域
恩智浦 - NXP 解复用器光电二极管PC
页数 文件大小 规格书
17页 134K
描述
Triple 2-channel analog multiplexer/demultiplexer

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74HCT4053D 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSSOP-16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.08
Is Samacsys：N模拟集成电路 - 其他类型：SPDT
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm湿度敏感等级：1
信道数量：1功能数量：3
端子数量：16标称断态隔离度：50 dB
通态电阻匹配规范：9 Ω最大通态电阻 (Ron)：180 Ω
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES最长断开时间：44 ns
最长接通时间：48 ns技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

74HCT4053D 数据手册

 浏览型号74HCT4053D的Datasheet PDF文件第1页浏览型号74HCT4053D的Datasheet PDF文件第3页浏览型号74HCT4053D的Datasheet PDF文件第4页浏览型号74HCT4053D的Datasheet PDF文件第5页浏览型号74HCT4053D的Datasheet PDF文件第6页浏览型号74HCT4053D的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Triple 2-channel analog  
multiplexer/demultiplexer  
74HC/HCT4053  
The 74HC/HCT4053 are triple 2-channel analog  
FEATURES  
multiplexers/demultiplexers with a common enable input  
(E). Each multiplexer/demultiplexer has two independent  
inputs/outputs (nY0 and nY1), a common input/output (nZ)  
and three digital select inputs (S1 to S3).  
• Low “ON” resistance:  
80 Ω (typ.) at VCC − VEE = 4.5 V  
70 Ω (typ.) at VCC − VEE = 6.0 V  
60 Ω (typ.) at VCC − VEE = 9.0 V  
With E LOW, one of the two switches is selected (low  
impedance ON-state) by S1 to S3. With E HIGH, all  
switches are in the high impedance OFF-state,  
independent of S1 to S3.  
• Logic level translation:  
to enable 5 V logic to communicate  
with ± 5 V analog signals  
• Typical “break before make” built in  
• Output capability: non-standard  
• ICC category: MSI  
VCC and GND are the supply voltage pins for the digital  
control inputs (S1, to S3, and E). The VCC to GND ranges  
are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The  
analog inputs/outputs (nY0 and nY1, and nZ) can swing  
between VCC as a positive limit and VEE as a negative limit.  
GENERAL DESCRIPTION  
V
CC − VEE may not exceed 10.0 V.  
The 74HC/HCT4053 are high-speed Si-gate CMOS  
devices and are pin compatible with the “4053” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
For operation as a digital multiplexer/demultiplexer, VEE is  
connected to GND (typically ground).  
QUICK REFERENCE DATA  
V
EE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
SYMBOL PARAMETER  
tPZH/ tPZL turn “ON” time  
TYPICAL  
CONDITIONS  
CL = 15 pF; RL = 1 kΩ; VCC = 5 V  
UNIT  
HC  
HCT  
E to VOS  
Sn to VOS  
17  
23  
ns  
21  
21  
ns  
t
PHZ/ tPLZ  
turn “OFF” time  
E to VOS  
18  
17  
3.5  
36  
20  
19  
3.5  
36  
ns  
ns  
pF  
pF  
Sn to VOS  
CI  
input capacitance  
CPD  
CS  
power dissipation capacitance per switch notes 1 and 2  
max. switch capacitance  
independent (Y)  
5
8
5
8
pF  
pF  
common  
(Z)  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi+∑ {(CL+CS) × VCC2 × fo} where:  
fi = input frequency in MHz; fo = output frequency in MHz  
∑ {(CL+CS) × VCC2 × fo} = sum of outputs  
CL = output load capacitance in pF; CS = max. switch capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC − 1.5 V  
December 1990  
2
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