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74HCT4053FT PDF预览

74HCT4053FT

更新时间: 2024-11-21 14:56:19
品牌 Logo 应用领域
东芝 - TOSHIBA 光电二极管
页数 文件大小 规格书
12页 341K
描述
Triple SPDT(1:2)/Analog Multiplexer, TSSOP16B

74HCT4053FT 数据手册

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74HCT4053FT  
CMOS Digital Integrated Circuits Silicon Monolithic  
74HCT4053FT  
1. Functional Description  
Triple 2-Channel Analog Multiplexer/Demultiplexer  
2. General  
The 74HCT4053FT is high speed CMOS ANALOG MULTIPLEXER/DEMULTIPLEXER fabricated with silicon  
gate CMOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining  
the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to  
High Speed CMOS. This inputs are compatible with TTL, NMOS and CMOS output voltage levels.  
The 74HCT4053FT has a 2 channel × 3 configuration.  
The digital signal to the control terminal turns "ON" the corresponding switch of each channel a large amplitude  
signal (VCC - VEE) can then be switched by the small logical amplitude (VCC - GND) control signal.  
For example, in the case of VCC = 5 V, GND = 0 V, VEE = -5 V, signals between -5 V and +5 V can be switched  
from the logical circuit with a single power supply of 5 V. As the ON-resistance of each switch is low, they can be  
connected to circuits with low input impedance.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
3. Features  
(1) Wide operating temperature range: Topr = -40 to 125  
(2) Low power dissipation: ICC = 4.0 µA (max) (VCC = 5.5 V, VEE = GND, Ta = 25 )  
(3) Compatible with TTL output: VIH = 2.0 V (min), VIL = 0.8 V (max)  
(4) Wide interfacing ability: LSTTL, NMOS, CMOS  
(5) Low ON-resistance: RON = 50 (typ.) at VCC - VEE = 9 V  
(6) High degree of linearity: THD = 0.020 % (typ.) at VCC - VEE = 9 V  
(7) Pin and function compatible with 4053B  
4. Packaging  
TSSOP16B  
Start of commercial production  
2020-07  
©2020  
Toshiba Electronic Devices & Storage Corporation  
2020-10-29  
Rev.1.0  
1

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