74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 — 14 September 2005
Product data sheet
1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4040B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
■ Multiple package options
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM JESD22-A114-C exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
■ Frequency dividing circuits
■ Time delay circuits
■ Control counters
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Type 74HC4040
tPHL, tPLH propagation delay
Conditions
Min Typ Max Unit
CP to Q0
CL = 15 pF; VCC = 5 V
CL = 15 pF; VCC = 5 V
-
-
14
8
-
-
ns
ns
Qn to Qn+1