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74HCT245A

更新时间： 2024-11-24 04:47:39
品牌 Logo 应用领域
安森美 - ONSEMI 总线收发器
页数 文件大小 规格书
9页 118K
描述
Octal 3−State Noninverting Bus Transceiver with LSTTL Compatible Inputs

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74HCT245A 数据手册

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MC74HCT245A  
Octal 3−State Noninverting  
Bus Transceiver with LSTTL  
Compatible Inputs  
High−Performance Silicon−Gate CMOS  
The MC74HCT245A is identical in pinout to the LS245. This  
device may be used as a level converter for interfacing TTL or NMOS  
outputs to High Speed CMOS inputs.  
http://onsemi.com  
The MC74HCT245A is a 3−state noninverting transceiver that is  
used for 2−way asynchronous communication between data buses.  
The device has an active−low Output Enable pin, which is used to  
place the I/O ports into high−impedance states. The Direction control  
determines whether data flows from A to B or from B to A.  
PDIP−20  
N SUFFIX  
CASE 738  
1
Features  
• Output Drive Capability: 15 LSTTL Loads  
• TTL/NMOS Compatible Input Levels  
• Outputs Directly Interface to CMOS, NMOS and TTL  
• Operating Voltage Range: 4.5 V to 5.5 V  
• Low Input Current: 1.0 mA  
SOIC−20W  
DW SUFFIX  
CASE 751D  
1
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
TSSOP−20  
DT SUFFIX  
CASE 948E  
• Chip Complexity: 304 FETs or 76 Equivalent Gates  
• Pb−Free Packages are Available  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
SOEIAJ−20  
F SUFFIX  
CASE 967  
A
B
DATA  
PORT  
DATA  
PORT  
1
PIN ASSIGNMENT  
1
DIRECTION  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
V
CC  
DIRECTION  
PIN 20 = V  
CC  
PIN 10 = GND  
19  
OUTPUT ENABLE  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OUTPUT ENABLE  
Figure 1. Logic Diagram  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
Design Criteria  
Internal Gate Count*  
Value  
76  
Units  
ea  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
1.0  
ns  
5.0  
mW  
pJ  
Speed Power Product  
0.005  
*Equivalent to a two−input NAND gate.  
FUNCTION TABLE  
Control Inputs  
GND 10  
11 B8  
Output Enable Direction  
Operation  
L
L
L
H
X
Data Transmitted from Bus B to Bus A  
Data Transmitted from Bus A to Bus B  
Buses Isolated (High−Impedance State)  
ORDERING INFORMATION  
See detailed ordering, shipping information, and marking  
information in the package dimensions section on page 6 of  
this data sheet.  
H
X = Don’t Care  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
January, 2007 − Rev. 10  
MC74HCT245A/D  
1234567...9

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