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74HC7030PW-T

更新时间： 2024-01-09 18:24:09

品牌	Logo	应用领域
恩智浦 - NXP		先进先出芯片
页数	文件大小	规格书
22页	175K
描述
IC 64 X 9 OTHER FIFO, PDSO28, SO-28, FIFO

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技术参数
数据手册

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74HC7030PW-T 技术参数

生命周期：	Obsolete	零件包装代码：	DIE
包装说明：	,	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.84	最长访问时间：	520 ns
周期时间：	71.428 ns	JESD-30 代码：	X-XUUC-N
内存密度：	576 bit	内存宽度：	9
功能数量：	1	字数：	64 words
字数代码：	64	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	64X9	可输出：	YES
封装主体材料：	UNSPECIFIED	封装形状：	UNSPECIFIED
封装形式：	UNCASED CHIP	并行/串行：	PARALLEL
认证状态：	Not Qualified	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

74HC7030PW-T 数据手册

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

FEATURES

Data outputs (Q₀to Q₈)

• Synchronous or asynchronous operation

• 3-state outputs

As there is no weighting of the outputs, any output can be

assigned as the MSB. The size of the FIFO memory can

be reduced from the 9 × 64 configuration as described for

data inputs. In a reduced format, the unused data output

pins must be left open circuit.

• Master-reset input to clear control functions

• 33 MHz (typ.) shift-in, shift-out rates with or without flags

• Very low power consumption

Master-reset (MR)

• Cascadable to 25 MHz (typ.)

When MR is LOW, the control functions within the FIFO

are cleared, and data content is declared invalid. The

data-in-ready (DIR) flag is set HIGH and the

data-out-ready (DOR) flag is set LOW. The output stage

remains in the state of the last word that was shifted out,

or in the random state existing at power-up.

• Readily expandable in word and bit dimensions

• Pinning arranged for easy board layout: input pins

directly opposite output pins

• Output capability: standard

• I_CCcategory: LSI

Status flag outputs (DIR, DOR)

GENERAL DESCRIPTION

Indication of the status of the FIFO is given by two status

flags, data-in-ready (DIR) and data-out-ready (DOR):

The 74HC/HCT7030 are high-speed Si-gate CMOS

devices specified in compliance with JEDEC standard

no. 7A.

DIR = HIGH indicates the input stage is empty and

ready to accept valid data

The 74HC/HCT7030 is an expandable, First-In First-Out

(FIFO) memory organized as 64 words by 9 bits. A 33 MHz

data-rate makes it ideal for high-speed applications. Even

at high frequencies, the I_CCdynamic is very low

DIR = LOW indicates that the FIFO is full or that a

previous shift-in operation is not complete

(busy)

(f_max= 18 MHz; V_CC= 5 V produces a dynamic I_CCof

80 mA). If the device is not continuously operating at f_max

then I_CCwill decrease proportionally.

DOR = HIGH assures valid data is present at the

outputs Q₀to Q₈(does not indicate that new

data is awaiting transfer into the output stage)

With separate controls for shift-in (SI) and shift-out (SO),

reading and writing operations are completely

DOR = LOW indicates the output stage is busy or

there is no valid data

independent, allowing synchronous and asynchronous

data transfers. Additional controls include a master-reset

input (MR) and an output enable input (OE). Flags for

data-in-ready (DIR) and data-out-ready (DOR) indicate the

status of the device.

Shift-in control (SI)

Data is loaded into the input stage on a LOW-to-HIGH

transition of SI. A HIGH-to-LOW transition triggers an

automatic data transfer process (ripple through). If SI is

held HIGH during reset, data will be loaded at the rising

edge of the MR signal.

Devices can be interconnected easily to expand word and

bit dimensions. All output pins are directly opposite the

corresponding input pins thus simplifying board layout in

expanded applications.

Shift-out control (SO)

A LOW-to-HIGH transition of SO causes the DOR flags to

go LOW. A HIGH-to-LOW transition of SO causes

upstream data to move into the output stage, and empty

locations to move towards the input stage (bubble-up).

INPUTS AND OUTPUTS

Data inputs (D₀to D₈)

As there is no weighting of the inputs, any input can be

assigned as the MSB. The size of the FIFO memory can

be reduced from the 9 × 64 configuration, i.e. 8 × 64,

7 × 64, down to 1 × 64, by tying unused data input pins to

Output enable (OE)

The outputs Q₀to Q₈are enabled when OE = LOW. When

OE = HIGH the outputs are in the high impedance

OFF-state.

_CCor GND.

December 1990

123 4 5 6 7...22

中文翻译

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与74HC7030PW-T相关器件

型号	品牌	描述	获取价格	数据表
74HC7030U	NXP	IC 64 X 9 OTHER FIFO, 520 ns, UUC, DIE, FIFO	获取价格
74HC7046A	NXP	Phase-locked-loop with lock detector	获取价格
74HC7046AD	ETC	Analog Phase-Locked Loop	获取价格
74HC7046AD,112	NXP	74HC(T)7046A - Phase-locked-loop with lock detector SOP 16-Pin	获取价格
74HC7046AD,118	NXP	74HC(T)7046A - Phase-locked-loop with lock detector SOP 16-Pin	获取价格
74HC7046ADB	NXP	IC PHASE LOCKED LOOP, PDSO16, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit	获取价格

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