Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
With the FIFO empty, the SO input can be held HIGH until
the SI control input is used. Following an SI pulse, data
moves through the FIFO to the output stage, resulting in
the DOR flag pulsing HIGH and a shift-out of data
occurring. The SO control must be made LOW before
additional data can be shifted out (see Fig.10).
FUNCTIONAL DESCRIPTION
Data input
Following power-up, the master-reset (MR) input is pulsed
LOW to clear the FIFO memory (see Fig.8). The
data-in-ready flag (DIR = HIGH) indicates that the FIFO
input stage is empty and ready to receive data. When DIR
is valid (HIGH), data present at D0 to D8 can be shifted-in
using the SI control input. With SI = HIGH, data is shifted
into the input stage and a busy indication is given by DIR
going LOW.
High-speed burst mode
If it is assumed that the shift-in/shift-out pulses are not
applied until the respective status flags are valid, it follows
that the shift-in/shift-out rates are determined by the status
flags. However, without the status flags a high-speed burst
mode can be implemented. In this mode, the
burst-in/burst-out rates are determined by the pulse widths
of the shift-in/shift-out inputs and burst rates of 35 MHz can
be obtained. Shift pulses can be applied without regard to
the status flags but shift-in pulses that would overflow the
storage capacity of the FIFO are not allowed (see Figs 11
and 12).
The data remains at the first location in the FIFO until SI is
set to LOW. With SI = LOW data moves through the FIFO
to the output stage, or to the last empty location. If the
FIFO is not full after the SI pulse, DIR again becomes valid
(HIGH) to indicate that space is available in the FIFO. The
DIR flag remains LOW if the FIFO is full (see Fig.6). The
SI pulse must be made LOW in order to complete the
shift-in process.
With the FIFO full, SI can be held HIGH until a shift-out
(SO) pulse occurs. Then, following a shift-out of data, an
empty location appears at the FIFO input and DIR goes
HIGH to allow the next data to be shifted-in. This remains
at the first FIFO location until SI again goes LOW (see
Fig.7).
Expanded format
With the addition of a logic gate, the FIFO is easily
expanded to increase word length (see Fig.17). The basic
operation and timing are identical to a single FIFO, with the
exception of an additional gate delay on the flag outputs. If
during application, the following occurs:
Data transfer
• SI is held HIGH when the FIFO is empty, some
additional logic is required to produce a composite DIR
pulse (see Figs 7 and 18).
After data has been transferred from the input stage of the
FIFO following SI = LOW, data moves through the FIFO
asynchronously and is stacked at the output end of the
register. Empty locations appear at the input end of the
FIFO as data moves through the device.
• SO is held HIGH when the FIFO is full, some additional
logic is required to produce a composite DOR pulse (see
Figs 10 and 18).
Due to the part-to-part spread of the ripple through time,
the flag signals of FIFOA and FIFOB will not always
coincide and the AND-gate will not produce a composite
flag signal. The solution is given in Fig.18.
Data output
The data-out-ready flag (DOR = HIGH) indicates that
there is valid data at the output (Q0 to Q8). The initial
master-reset at power-on (MR = LOW) sets DOR to LOW
(see Fig.8). After MR = HIGH, data shifted into the FIFO
moves through to the output stage causing DOR to go
HIGH. As the DOR flag goes HIGH, data can be
shifted-out using the SO control input. With SO = HIGH,
data in the output stage is shifted out and a busy indication
is given by DOR going LOW. When SO is made LOW,
data moves through the FIFO to fill the output stage and an
empty location appears at the input stage. When the
output stage is filled DOR goes HIGH, but if the last of the
valid data has been shifted out leaving the FIFO empty the
DOR flag remains LOW (see Fig.9). With the FIFO empty,
the last word that was shifted-out is latched at the output
Q0 to Q8.
The “7030” is easily cascaded to increase the word
capacity and no external components are needed. In the
cascaded configuration, all necessary communications
and timing are performed by the FIFOs. The
intercommunication speed is determined by the minimum
flag pulse widths and the flag delays. The data rate of
cascaded devices is typically 25 MHz. Word-capacity can
be expanded to and beyond 128-words × 9-bits (see
Fig.19).
December 1990
6
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