Datasheet > 74HC595D-Q100

74HC595D-Q100

更新时间： 2023-09-03 20:28:42

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
20页	295K
描述
8-bit serial-in, serial or parallel-out shift register with output latches; 3-stateProduction

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74HC595D-Q100 数据手册

74HC595-Q100; 74HCT595-Q100

8-bit serial-in, serial or parallel-out shift register with output

latches; 3-state

Rev. 4 — 11 March 2020

Product data sheet

1. General description

The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with

a storage register and 3-state outputs. Both the shift and storage register have separate clocks.

The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an

asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the

LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the

storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected

together, the shift register will always be one clock pulse ahead of the storage register. Data in the

storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on

OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does

not affect the state of the registers. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

8-bit serial input

8-bit serial or parallel output

Storage register with 3-state outputs

Shift register with direct clear

100 MHz (typical) shift out frequency

Complies with JEDEC standard no. 7A

Input levels:

•

For 74HC595-Q100: CMOS level

For 74HCT595-Q100: TTL level

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

Multiple package options

DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

3. Applications

•

Serial-to-parallel data conversion

Remote control holding register

12 3 4 5 6 7...20

下载PDF

与74HC595D-Q100相关器件

型号	品牌	描述	获取价格	数据表
74HC595DR2G	ONSEMI	8−Bit Serial−Input/Serial or Parallel−Output Shift Register with Latched	获取价格
74HC595DTR2G	ONSEMI	8−Bit Serial−Input/Serial or Parallel−Output Shift Register with Latched	获取价格
74HC595N	NXP	8-bit serial-in/serial or parallel-out shift register with output latches; 3-state	获取价格
74HC595N,112	NXP	74HC(T)595 - 8-bit serial-in, serial or parallel-out shift register with output latches; 3	获取价格
74HC595P	TGS	8-Bit Shift Registers with Output Latches	获取价格
74HC595PW	NEXPERIA	8-bit serial-in, serial or parallel-out shift	获取价格