Datasheet > 74HC4520D-Q100

74HC4520D-Q100

更新时间： 2024-11-30 01:16:03

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	226K
描述
Dual 4-bit synchronous binary counter

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74HC4520D-Q100 数据手册

74HC4520-Q100;

74HCT4520-Q100

Dual 4-bit synchronous binary counter

Rev. 2 — 14 February 2019

Product data sheet

1. General description

The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters

with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions

(nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either

the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW

transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the

counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the

counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It

enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Complies with JEDEC standard no. 7A

Input levels:

•

For 74HC4520-Q100: CMOS level

For 74HCT4520-Q100: TTL level

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

3. Applications

•

Multistage synchronous counting

Multistage asynchronous counting

Frequency dividers

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC4520D-Q100

74HCT4520D-Q100

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

12 3 4 5 6 7...13

中文翻译

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