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74HC4510PW-T PDF预览

74HC4510PW-T

更新时间: 2024-02-16 11:55:48
品牌 Logo 应用领域
恩智浦 - NXP 计数器
页数 文件大小 规格书
12页 103K
描述
IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16, Counter

74HC4510PW-T 技术参数

生命周期:Active包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.33其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDSO-G16长度:5 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):66 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:20 MHz
Base Number Matches:1

74HC4510PW-T 数据手册

 浏览型号74HC4510PW-T的Datasheet PDF文件第6页浏览型号74HC4510PW-T的Datasheet PDF文件第7页浏览型号74HC4510PW-T的Datasheet PDF文件第8页浏览型号74HC4510PW-T的Datasheet PDF文件第10页浏览型号74HC4510PW-T的Datasheet PDF文件第11页浏览型号74HC4510PW-T的Datasheet PDF文件第12页 
Philips Semiconductors  
Product specification  
BCD up/down counter  
74HC/HCT4510  
T
amb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to +85 40 to +125  
min. typ. max. min. max. min. max.  
trem  
trem  
tsu  
tsu  
tsu  
th  
removal time  
MR to CP  
23  
17  
20  
20  
20  
5
13  
10  
12  
6
29  
21  
25  
25  
25  
5
35  
26  
30  
30  
30  
5
ns  
4.5 Fig.10  
4.5 Fig.10  
4.5 Fig.8  
4.5 Fig.8  
4.5 Fig.11  
4.5 Fig.8  
4.5 Fig.11  
4.5 Fig.8  
4.5 Fig.7  
removal time  
PL to CP  
ns  
set-up time  
UP/DN to CP  
ns  
set-up time  
CE to CP  
ns  
set-up time  
Dn to PL  
6
ns  
hold time  
CE to CP  
0
ns  
th  
hold time  
Dn to PL  
5
0
5
5
ns  
th  
hold time  
UP/DN to CP  
0
5  
53  
0
0
ns  
fmax  
maximum clock pulse 30  
frequency  
24  
20  
MHz  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.8 Waveforms showing the set-up and hold  
times from count enable (CE) and  
up/down (UP/DN) control inputs to the  
clock pulse (CP), the propagation delays  
from UP/DN, CE to TC.  
Fig.7 Waveforms showing the clock (CP) to  
output (Qn) and terminal count (TC)  
propagation delays, the clock pulse width  
and the maximum clock pulse frequency.  
December 1990  
9

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