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74HC4067D,653 PDF预览

74HC4067D,653

更新时间: 2024-11-09 15:29:23
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
29页 158K
描述
74HC(T)4067 - 16-channel analog multiplexer/demultiplexer SOP 24-Pin

74HC4067D,653 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP24,.4
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:6.96
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXERJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:15.4 mm
湿度敏感等级:1信道数量:16
功能数量:1端子数量:24
标称断态隔离度:50 dB通态电阻匹配规范:6 Ω
最大通态电阻 (Ron):130 Ω最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2/10 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Multiplexer or Switches最大供电电流 (Isup):0.32 mA
最大供电电压 (Vsup):10 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):9 V表面贴装:YES
最长断开时间:57 ns最长接通时间:63 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

74HC4067D,653 数据手册

 浏览型号74HC4067D,653的Datasheet PDF文件第2页浏览型号74HC4067D,653的Datasheet PDF文件第3页浏览型号74HC4067D,653的Datasheet PDF文件第4页浏览型号74HC4067D,653的Datasheet PDF文件第5页浏览型号74HC4067D,653的Datasheet PDF文件第6页浏览型号74HC4067D,653的Datasheet PDF文件第7页 
74HC4067; 74HCT4067  
16-channel analog multiplexer/demultiplexer  
Rev. 03 — 15 October 2007  
Product data sheet  
1. General description  
The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible  
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.  
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four  
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent  
inputs/outputs (Y0 to Y15) and a common input/output (Z).  
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with  
one side connected to an independent input/output (Y0 to Y15) and the other side  
connected to a common input/output (Z).  
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low  
impedance ON-state). All unselected switches are in the high-impedance OFF-state.  
With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins  
S0 to S3.  
The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit  
and GND as a negative limit. VCC to GND may not exceed 10 V.  
2. Features  
I Low ON resistance:  
N 80 (typical) at VCC = 4.5 V  
N 70 (typical) at VCC = 6.0 V  
N 60 (typical) at VCC = 9.0 V  
I Typical ‘break before make’ built-in  
3. Applications  
I Analog multiplexing and demultiplexing  
I Digital multiplexing and demultiplexing  
I Signal gating  
 
 
 

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