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74HC1G02GV PDF预览

74HC1G02GV

更新时间: 2024-11-19 11:12:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
10页 201K
描述
2-input NOR gateProduction

74HC1G02GV 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2.9 mm逻辑集成电路类型:NOR GATE
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):135 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.5 mmBase Number Matches:1

74HC1G02GV 数据手册

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74HC1G02; 74HCT1G02  
2-input NOR gate  
Rev. 5 — 21 January 2022  
Product data sheet  
1. General description  
The74HC1G02; 74HCT1G02 is a single 2-input NOR gate. Inputs include clamp diodes. This  
enables the use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
Symmetrical output impedance  
High noise immunity  
Balanced propagation delays  
Input levels:  
For 74HC1G02: CMOS level  
For 74HCT1G02: TTL level  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
HBM JESD22-A114-A exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40° C to +85° C and -40° C to +125° C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +125 °C  
Name  
Description  
Version  
74HC1G02GW  
74HCT1G02GW  
74HC1G02GV  
74HCT1G02GV  
TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1  
body width 1.25 mm  
-40 °C to +125 °C  
SC-74A  
plastic surface-mounted package; 5 leads  
SOT753  
 
 
 
 

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