5秒后页面跳转
74HC1G00 PDF预览

74HC1G00

更新时间: 2024-01-17 14:23:45
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
16页 75K
描述
2-input NAND gate

74HC1G00 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SC-88A, 5 PIN针数:5
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.08Is Samacsys:N
系列:HC/UHJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:NAND GATE湿度敏感等级:1
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):135 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

74HC1G00 数据手册

 浏览型号74HC1G00的Datasheet PDF文件第1页浏览型号74HC1G00的Datasheet PDF文件第3页浏览型号74HC1G00的Datasheet PDF文件第4页浏览型号74HC1G00的Datasheet PDF文件第5页浏览型号74HC1G00的Datasheet PDF文件第6页浏览型号74HC1G00的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
2-input NAND gate  
74HC1G00; 74HCT1G00  
FEATURES  
DESCRIPTION  
Wide supply voltage range from 2.0 to 6.0 V  
Symmetrical output impedance  
High noise immunity  
The 74HC1G/HCT1G00 is a high speed Si-gate CMOS  
device.  
The 74HC1G/HCT1G00 provides the 2-input NAND  
function. The standard output currents are 12 compared to  
the 74HC/HCT00.  
Low power dissipation  
Balanced propagation delays  
Very small 5 pins package  
Output capability: standard.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf 6.0 ns.  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC1G  
HCT1G  
10  
tPHL/tPLH propagation delay A, B to Y  
CL = 15 pF; VCC = 5 V  
7
CI  
input capacitance  
1.5  
19  
1.5  
21  
pF  
pF  
CPD  
power dissipation capacitance  
notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
(CL × VCC2 × fo) = sum of outputs.  
2. For HC1G the condition is VI = GND to VCC  
.
For HCT1G the condition is VI = GND to VCC 1.5 V.  
FUNCTION TABLE  
See note 1.  
INPUTS  
OUTPUT  
Y
A
B
L
L
L
H
L
H
H
H
L
H
H
H
Note  
1. H = HIGH voltage level;  
L = LOW voltage level.  
2002 May 15  
2

与74HC1G00相关器件

型号 品牌 描述 获取价格 数据表
74HC1G00GV NXP 2-input NAND gate

获取价格

74HC1G00GV NEXPERIA 2-input NAND gateProduction

获取价格

74HC1G00GV,125 NXP 74HC(T)1G00 - 2-input NAND gate TSOP 5-Pin

获取价格

74HC1G00GV-Q100 NEXPERIA 2-input NAND gate

获取价格

74HC1G00GV-Q100,125 NXP NAND Gate, HC/UH Series, 1-Func, 2-Input, CMOS, PDSO5

获取价格

74HC1G00GW NXP 2-input NAND gate

获取价格