Datasheet > 74HC195NB

74HC195NB

更新时间： 2023-01-03 07:06:26

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管输出元件
页数	文件大小	规格书
9页	67K
描述
IC HC/UH SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, Shift Register

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74HC195NB 数据手册

Philips Semiconductors

Product speciﬁcation

4-bit parallel access shift register

74HC/HCT195

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3V; V_I= GND to 3 V.

Fig.7 Waveforms showing the master reset

(MR) pulse width, the master reset to output

(Q_n) propagation delays and the master

reset to clock (CP) removal time

Fig.6 Waveforms showing the clock (CP) to

output (Q_n) propagation delays, the clock

pulse width, the output transition times and

the maximum clock frequency.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3V; V_I= GND to 3 V.

Fig.8 Waveforms showing the data set-up

and hold times for J, K and D_ninputs.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3V; V_I= GND to 3 V.

Fig.9 Waveforms showing the set-up and hold

times from the parallel enable input

(PE) to the clock (CP).

December 1990

1...5 6 789

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