74HC138N,652 PDF预览

74HC138N,652

更新时间: 2025-09-21 19:23:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
19页 209K
描述
电流 - 输出高、低:5.2mA;最小工作电压(V):2V;最大工作电压(V):6V;最大输出电流(mA):5.2mA;元器件封装:16-DIP;

74HC138N,652 数据手册

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74HC138; 74HCT138  
3-to-8 line decoder/demultiplexer; inverting  
Rev. 5 — 26 January 2015  
Product data sheet  
1. General description  
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2)  
to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs  
(E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.  
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines)  
decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output  
demultiplexer by using one of the active LOW enable inputs as the data input and the  
remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of  
current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Complies with JEDEC standard no. 7A  
Input levels:  
For 74HC138: CMOS level  
For 74HCT138: TTL level  
Demultiplexing capability  
Multiple input enable for easy expansion  
Ideal for memory chip select decoding  
Active LOW mutually exclusive outputs  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC138N  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
DIP16  
plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
74HCT138N  
74HC138D  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
SOT338-1  
74 HCT138D  
74HC138DB  
74HCT138DB  
SSOP16  
plastic shrink small outline package; 16 leads;  
body width 5.3 mm  

74HC138N,652 替代型号

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CD74HC138EE4 TI

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