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74F569PCQR PDF预览

74F569PCQR

更新时间: 2024-11-09 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
9页 86K
描述
Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL, PDIP20, PLASTIC, DIP-20

74F569PCQR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:N其他特性:TCO OUTPUT; CLOCKED CARRY OUTPUT
计数方向:BIDIRECTIONAL系列:F/FAST
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:24.895 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:115 MHzBase Number Matches:1

74F569PCQR 数据手册

 浏览型号74F569PCQR的Datasheet PDF文件第2页浏览型号74F569PCQR的Datasheet PDF文件第3页浏览型号74F569PCQR的Datasheet PDF文件第4页浏览型号74F569PCQR的Datasheet PDF文件第5页浏览型号74F569PCQR的Datasheet PDF文件第6页浏览型号74F569PCQR的Datasheet PDF文件第7页 
April 1988  
Revised August 1999  
74F569  
4-Bit Bidirectional Counter with 3-STATE Outputs  
General Description  
Features  
The 74F569 is a fully synchronous, reversible counter with  
3-STATE outputs. The 74F569 is a binary counter, featur-  
ing preset capability for programmable operation, carry loo-  
kahead for easy cascading, and a U/D input to control the  
direction of counting. For maximum flexibility there are both  
synchronous and master asynchronous reset inputs as well  
as both Clocked Carry (CC) and Terminal Count (TC) out-  
puts. All state changes except Master Reset are initiated by  
the rising edge of the clock. A HIGH signal on the Output  
Synchronous counting and loading  
Lookahead carry capability for easy cascading  
Preset capability for programmable operation  
3-STATE outputs for bus organized systems  
Enable (OE) input forces the output buffers into the high  
impedance state but does not prevent counting, resetting  
or parallel loading.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F569SC  
74F569SJ  
74F569PC  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
FAST is a registered trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009565  
www.fairchildsemi.com  

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