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74F399 PDF预览

74F399

更新时间: 2024-11-06 04:01:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 78K
描述
Quad 2-Port Register

74F399 数据手册

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April 1988  
Revised January 2004  
74F399  
Quad 2-Port Register  
General Description  
Features  
The 74F399 is the logical equivalent of a quad 2-input mul-  
tiplexer feeding into four edge-triggered flip-flops. A com-  
mon Select input determines which of the two 4-bit words is  
accepted. The selected data enters the flip-flops on the ris-  
ing edge of the clock.  
Select inputs from two data sources  
Fully positive edge-triggered operation  
Ordering Code:  
Order Number Package Number  
Package Description  
74F399SC  
74F399SJ  
74F399PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
S
Common Select Input  
20 µA/0.6 mA  
20 µA/0.6 mA  
20 µA/0.6 mA  
20 µA/0.6 mA  
1 mA/20 mA  
CP  
Clock Pulse Input (Active Rising Edge)  
Data Inputs from Source 0  
Data Inputs from Source 1  
Register True Outputs  
1.0/1.0  
I
0aI0d  
1.0/1.0  
I
1aI1d  
1.0/1.0  
QaQd  
50/33.3  
© 2004 Fairchild Semiconductor Corporation  
DS009533  
www.fairchildsemi.com  

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